MCP4716 datasheet(33/70 Pages) MICROCHIP

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 2012 Microchip Technology Inc.

DS25154A-page 33

MCP47A1

5.3

Serial Commands

The MCP47A1 devices support two serial commands.

These commands are:

•

Write Operation

•

Read Operations

The I2C command formats have been defined to

support the SMBus version 2.0 Write Byte/Word

Protocol formats

and

Read

Byte/Word Protocol

formats. The SMBus specification that defines this

operation is Section 5 of the Version 2.0 document

(August 3, 2000).

This protocol format may be convenient for customers

using library routines for the I2C bus, where all they

need to do is specify the command (read, write, ...) with

the Device Address, the Register Address, and the

Data.

5.3.1

WRITE OPERATION

The write operation requires the START condition,

Control

Byte,

Acknowledge,

Command

Code,

Acknowledge, Data Byte, Acknowledge and STOP (or

RESTART) condition. The Control (Slave Address)

Byte requires the R/W bit equal to a logic zero (R/W =

“0”

) to generate a write sequence. The MCP47A1 is

responsible for generating the Acknowledge (A) bits.

Data is written to the MCP47A1 after every byte

transfer (during the A bit). If a STOP or RESTART

condition is generated during a data transfer (before

the A bit), the data will not be written to MCP47A1.

Data bytes may be written after each Acknowledge.

The command is terminated once a Stop (P) condition

occurs. Refer to Figure 5-11 for the single byte write

sequence and Figure 5-12 for the generic (multi-byte)

write sequence. For a single byte write, the master

sends a STOP or RESTART condition after the 1st data

byte is sent.

The MSb of each Data Byte is a don’t care, since the

wiper register is only 7-bits wide.

The command is terminated once a Stop (P) or Restart

(S) condition occurs.

Figure 5-13 shows the I2C write communication

behavior of the Master Device and the MCP47A1

device and the resultant I2C bus values.

5.3.2

READ OPERATIONS

The read operation requires the START condition,

Control

Byte,

Acknowledge,

Command

Code,

Acknowledge,

Restart

Condition,

Control

Byte,

Acknowledge, Data Byte, the master generating the

A and STOP (or RESTART) condition. The first Control

Byte requires the R/W bit equal to a logic zero (R/W =

“0”

) to write the Command Code, while the second

Control Byte requires the R/W bit equal to a logic one

(R/W = “1”) to generate a read sequence. The

MCP47A1 will A the Slave Address Byte and A all the

Data Bytes. The I2C Master will A the Slave Address

Byte and the last Data Byte. If there are multiple Data

Bytes, the I2C Master will A all Data Bytes except the

last Data Byte (which it will A).

The MCP47A1 maintains control of the SDA signal until

all data bits have been clocked out.

The command is terminated once a Stop (P) or Restart

(S) condition occurs. Refer to Figure 5-14 for the read

command sequence. For a single read, the master

sends a STOP or RESTART condition after the 1st data

byte (and A bit) is sent from the slave.

The MSb of each Data Byte is always a “0”, since the

wiper register is only 7-bits wide.

Figure 5-15 shows the I2C read communication

behavior of the Master Device and the MCP47A1

device and the resultant I2C bus values.

Note:

A command code with a non-zero value

will cause the data not to be written to the

wiper register

Note:

A command code with a non-zero value

will cause the data not to be read from the

wiper register

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