List of figures

Figure 1.

Pin connections (top view) ............................................................ 2

Figure 2.

Supply current vs supply voltage....................................................... 10

Figure 3.

Input offset voltage distribution at VCC = 5 V ............................................... 10

Figure 4.

Input offset voltage distribution at VCC = 3.3 V ............................................. 10

Figure 5.

Input offset voltage distribution at VCC = 2.2 V ............................................. 10

Figure 6.

Input offset voltage distribution at VCC = 5 V, T = 150 °C ...................................... 10

Figure 7.

Input offset voltage distribution at VCC = 5 V, T = -40 °C ...................................... 10

Figure 8.

Input offset voltage distribution at VCC=2.2 V, T = 150 °C ...................................... 11

Figure 9.

Input offset voltage distribution at VCC=2.2 V, T = -40 °C ...................................... 11

Figure 10.

Input offset voltage vs supply voltage ................................................... 11

Figure 11.

Input offset voltage vs input common mode at VCC= 5 V ...................................... 11

Figure 12.

Input offset voltage vs input common mode at VCC= 3.3 V ..................................... 11

Figure 13.

Input offset voltage vs input common mode at VCC= 2.2 V ..................................... 11

Figure 14.

Input offset voltage vs temperature ..................................................... 12

Figure 15.

VOH vs supply voltage .............................................................. 12

Figure 16.

VOL vs supply voltage .............................................................. 12

Figure 17.

Output current vs output voltage at VCC = 5 V.............................................. 12

Figure 18.

Output current vs. output voltage at VCC = 2.2 V ............................................ 12

Figure 19.

Input bias current vs common-mode at VCC = 5 V ........................................... 12

Figure 20.

Input bias current vs. temperature at VCC = 5 V ............................................ 13

Figure 21.

Output rail linearity ................................................................ 13

Figure 22.

Bode diagram at VCC=5 V ........................................................... 13

Figure 23.

Bode diagram at VCC=2.2 V .......................................................... 13

Figure 24.

Bode diagram at VCC=3.3 V .......................................................... 13

Figure 25.

Open loop gain vs frequency ......................................................... 13

Figure 26.

Positive slew rate vs supply voltage..................................................... 14

Figure 27.

Negative slew rate vs supply voltage .................................................... 14

Figure 28.

Noise 0.1 – 10 Hz vs time ........................................................... 14

Figure 29.

Noise vs frequency ................................................................ 14

Figure 30.

Output overshoot vs load capacitance ................................................... 14

Figure 31.

Small signal VCC = 5 V ............................................................. 14

Figure 32.

Small signal VCC = 2.2 V ............................................................ 15

Figure 33.

Large signal VCC = 5 V ............................................................. 15

Figure 34.

Large signal VCC = 2.2 V ............................................................ 15

Figure 35.

Negative overvoltage recovery VCC = 2.2 V ............................................... 15

Figure 36.

Positive overvoltage recovery VCC = 5 V ................................................. 15

Figure 37.

Output impedance vs frequency ....................................................... 15

Figure 38.

Settling time positive step (-2 V to 0 V)................................................... 16

Figure 39.

Settling time negative step (2 V to 0 V) .................................................. 16

Figure 40.

Settling time positive step (-0.8 V to 0 V) ................................................. 16

Figure 41.

Settling time negative step (0.8 V to 0 V) ................................................. 16

Figure 42.

Maximum output voltage vs frequency ................................................... 16

Figure 43.

Crosstalk vs frequency ............................................................. 16

Figure 44.

PSSR vs frequency ................................................................ 17

Figure 45.

SO8 package outline ............................................................... 18

Figure 46.

SOT23-5 package outline ........................................................... 20

TSZ181H, TSZ182H

List of figures

DS13229 - Rev 2

page 25/26