ADTR1107ACCZ-R7 datasheet(24/28 Pages) AD

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ADTR1107

Data Sheet

Rev. A | Page 24 of 28

APPLICATIONS INFORMATION

The basic connections for operating the ADTR1107 are shown

in Figure 89. The power amplifier on the transmit path is biased

with +5 V on the VDD_PA pin and a voltage from −1.75 V to

−0.25 V is applied to the VGG_PA pin to achieve 220 mA

quiescent current.

The LNA on the receive path operates as either self biased or

external biased mode. For self biased mode, apply 3.3 V to the

VDD_LNA pin and leave the VGG_LNA pin supplied with 0 V

or connected to ground. For external biased mode, apply +3.3 V

to the VDD_LNA pin and adjust the VGG_LNA pin with a voltage

range of −1.5 V to 0 V to achieve the desired IDQ_PA.

The SPDT switch is biased with +3.3 V on the VDD_SW pin

and −3.3 V on the VSS_SW pin. The CTRL_SW pin sets the

path state shown in Table 8. High logic state is set at 3.3 V and

low logic state is set at 0 V.

All required decoupling capacitors for the dc power supply

lines are internal to the ADTR1107.

RECOMMENDED BIAS SEQUENCING

The recommended bias sequence during transmit state

power-up is as follows:

Connect all GND pins to ground.

Set the VDD_SW pin to 3.3 V.

Set the VSS_SW pin to −3.3 V.

Set the CTRL_SW pin to 0 V.

Set the VGG_LNA pin to 0 V.

Set the VDD_LNA pin to 0 V.

Set the VGG_PA pin to −1.75 V.

Set the VDD_PA pin to 5 V.

Increase the VGG_PA voltage to achieve the desired

IDQ_PA.

10. Apply the RF signal to the TX_IN pin.

The recommended transmit state bias sequence during

power-down is as follows:

Turn off the RF signal.

Decrease the VGG_PA voltage to −1.75 V.

Set the VDD_PA pin to 0 V.

Set the VSS_SW pin to 0 V.

Set the VDD_SW pin to 0 V.

The recommended bias sequence during receive state power-up

is as follows:

Connect all GND pins to ground.

Set the VDD_SW pin to 3.3 V.

Set the VSS_SW pin to −3.3 V.

Set the CTRL_SW pin to 3.3 V.

Set the VGG_PA pin to −1.75 V.

Set the VDD_PA pin to 0 V.

Set the VGG_LNA pin to 0 V.

Set the VDD_LNA pin to 3.3 V.

Apply the RF signal to the ANT pin.

The recommended receive state bias sequence during

power-down is as follows:

Turn off the RF signal.

Set the VDD_LNA pin to 0 V.

Set the CTRL_SW pin to 0 V.

Set the VSS_SW pin to 0 V.

Set the VDD_SW pin to 0 V.

All measurements and data shown in this data sheet were taken

using the typical application circuit (see Figure 89) and biased

per the conditions in this section, unless otherwise noted. The

bias conditions described in this section are the operating

points recommended to optimize the overall device performance.

Operation using other bias conditions can result in performance

that differs from what is shown in the Typical Performance

Characteristics section. To obtain optimal performance while

not damaging the device, follow the recommended biasing

sequences described in this section and adhere to the values

shown in the Absolute Maximum Ratings section.

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