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LD57100J100R датащи(PDF) 8 Page - STMicroelectronics

номер детали LD57100J100R
подробное описание детали  1 A ultra low-dropout LDO with bias
PDF  21 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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LD57100J100R датащи(HTML) 8 Page - STMicroelectronics

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6
Application information
6.1
VBIAS pin voltage requirements
The bias input is the supply of the internal driving and control circuitry. In order to assure a proper biasing of the
N-channel power element, the bias pin must have a minimum voltage of 3.0 V and be 1.6 V (typically) higher than
the output. If VIN supply voltage meets these requirements then the bias pin can be tied to VIN.
6.2
Output discharge function
The LD57100 integrates a MOSFET connected between VOUT and GND. This transistor is activated when the
EN pin goes to low logic level and has the function to quickly discharge the output capacitor when the device is
disabled by the user.
6.3
Short-circuit and current limitation
The LD57100 is protected against short-circuit on the output. The load current is limited to the maximum value of
ILIM when VOUT is equal to 90% of its nominal value.
6.4
VOUT setting (adjustable version)
In the LD57100 adjustable version, the desired output voltage is set according to the formula below:
VOUT=VREF× 1+R1R2
(1)
where R2 cannot be higher than 500 kΩ.
Please, refer to Figure 5. Typical application for adjustable version for R1 and R2 connections.
6.5
Thermal protection
Thermal protection works when the junction temperature reaches 160 °C typical. At this point, the output of the
IC shuts down. As soon as the junction temperature falls below the thermal hysteresis value, the device starts
working again.
In order to calculate the maximum power that the device can dissipate, keeping the junction temperature below
the maximum operating value, the following formula is used:
PDMAX= 85−TAMB/RtℎJA
(2)
6.6
Input and output capacitors
The LD57100 requires external capacitors to assure the regulator control loop stability.
Any good quality ceramic capacitor can be used, however the X5R and the X7R are suggested since they
guarantee a very stable combination of capacitance and ESR all over the temperature range.
It is recommended to place the input/output capacitors as close as possible to the relative pins. The LD57100
requires a VIN capacitor with a minimum value of 1 μF and a VBIAS capacitor of 100 nF minimum. These
capacitors must be placed as close as possible to the input pins of the device and returned to a clean analog
ground.
The control loop is designed to be stable with any good quality output ceramic capacitor (such as: X5R/X7R
types) with a minimum value of 1.0 μF and equivalent series resistance in the [3 – 300 mΩ] range. It is important
to highlight that the output capacitor must maintain its capacitance and ESR in the stable region over the
full operating temperature, load and input voltage ranges, to assure stability. Therefore, capacitance and ESR
variations must be taken into account in the design phase to be sure that the device works in the expected
stability region.
LD57100
Application information
DS13123 - Rev 5
page 8/21



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