V+ to assert a logic high on any I/O port. For example,

a MAX7321 operating from a +5V supply may not rec-

ognize a +3.3V nominal logic high. One solution for

input-level translation is to drive MAX7321 I/Os from

open-drain outputs. Use a pullup resistor to V+ or a

higher supply to ensure a high logic voltage of greater

than 0.7 x V+.

Port-Output Port-Level Translation

The open-drain output architecture allows for level

translation to higher or lower voltages than the

MAX7321’s supply. Use an external pullup resistor on

any output to convert the high-impedance logic-high

condition to a positive voltage level. The resistor can be

connected to any voltage up to +6V, and the resistor

value chosen to ensure no more than 20mA is sunk in

the logic-low condition. For interfacing CMOS inputs, a

pullup resistor value of 220k

Ω is a good starting point.

Use a lower resistance to improve noise immunity, in

applications where power consumption is less critical,

or where a faster rise time is needed for a given capac-

itive load.

Hot Insertion

RST, SCL, SDA, AD0, and AD2 and the P0–P7 I/Os

remain high impedance with up to +6V asserted on

them when the MAX7321 is powered down (V+ = 0).

The MAX7321 can therefore be used in hot-swap appli-

cations.

Each of the I/O P0–P7 has a protection diode to GND

than GND, the protection diode clamps the voltage to a

diode drop below GND.

______________________________________________________________________________________

13

D

S

G

S

D

G

PORT

PULLUP

ENABLE

INPUT

OUTPUT

40k

Ω

MAX7321

V+

V+

Figure 10. MAX7321 Input Port Structure

CONTROL

P0

P3

P2

P1

P4

P5

P6

P7

INT

I/O

PORTS

GND

POWER-

ON RESET

INPUT

FILTER

V+

RST

SDA

SCL

AD2

AD0

MAX7321

Functional Diagram