DSPIC30F2011 datasheet(113/207 Pages) MICROCHIP

113 / 207 page

Preliminary

DS70139C-page 111

dsPIC30F2011/2012/3012/3013

16.4

Programming the Start of

Conversion Trigger

The conversion trigger will terminate acquisition and

start the requested conversions.

The SSRC<2:0> bits select the source of the conver-

sion trigger. The SSRC bits provide for up to 4 alternate

sources of conversion trigger.

When SSRC<2:0> = 000, the conversion trigger is

under software control. Clearing the SAMP bit will

cause the conversion trigger.

When SSRC<2:0> = 111 (Auto-Start mode), the con-

version trigger is under A/D clock control. The SAMC

bits select the number of A/D clocks between the start

of acquisition and the start of conversion. This provides

the fastest conversion rates on multiple channels.

SAMC must always be at least 1 clock cycle.

Other trigger sources can come from timer modules or

external interrupts.

16.5

Aborting a Conversion

Clearing the ADON bit during a conversion will abort

the current conversion and stop the sampling sequenc-

ing until the next sampling trigger. The ADCBUF will not

be updated with the partially completed A/D conversion

sample. That is, the ADCBUF will continue to contain

the value of the last completed conversion (or the last

value written to the ADCBUF register).

If the clearing of the ADON bit coincides with an auto-

start, the clearing has a higher priority and a new

conversion will not start.

After the A/D conversion is aborted, a 2 TAD wait is

required before the next sampling may be started by

setting the SAMP bit.

16.6

Selecting the A/D Conversion

Clock

The A/D conversion requires 14 TAD. The source of the

A/D conversion clock is software selected, using a

six-bit counter. There are 64 possible options for TAD.

EQUATION 16-1:

A/D CONVERSION CLOCK

The internal RC oscillator is selected by setting the

ADRC bit.

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 667 nsec (for VDD = 5V). Refer to the Electrical

Specifications section for minimum TAD under other

operating conditions.

Example 16-1 shows a sample calculation for the

ADCS<5:0> bits, assuming a device operating speed

of 30 MIPS.

EXAMPLE 16-1:

A/D CONVERSION CLOCK

AND SAMPLING RATE

CALCULATION

16.7

A/D Acquisition Requirements

The analog input model of the 12-bit A/D converter is

shown in Figure 16-2. The total sampling time for the A/

D is a function of the internal amplifier settling time and

the holding capacitor charge time.

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the voltage level on the analog input

pin. The source impedance (RS), the interconnect

impedance (RIC), and the internal sampling switch

(RSS) impedance combine to directly affect the time

required to charge the capacitor CHOLD. The combined

impedance of the analog sources must therefore be

small enough to fully charge the holding capacitor

within the chosen sample time. To minimize the effects

of pin leakage currents on the accuracy of the A/D con-

verter, the maximum recommended source imped-

ance, RS, is 2.5 k

Ω. After the analog input channel is

selected (changed), this sampling function must be

completed prior to starting the conversion. The internal

holding capacitor will be in a discharged state prior to

each sample operation.

TAD = TCY * (0.5*(ADCS<5:0> + 1))

Minimum TAD = 667 nsec

ADCS<5:0> = 2

– 1

TAD

TCY

TCY = 33 .33 nsec (30 MIPS)

= 2 •

– 1

667 nsec

33.33 nsec

= 39

Therefore,

Set ADCS<5:0> = 39

Actual TAD =

(ADCS<5:0> + 1)

TCY

(39 + 1)

33.33 nsec

= 667 nsec

If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’

Since,

Sampling Time = Acquisition Time + Conversion Time

= 1 TAD + 14 TAD

= 15 x 667 nsec

Therefore,

Sampling Rate =

= ~100 kHz

(15 x 667 nsec)

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