ADGS1409BCPZ datasheet(26/34 Pages) AD

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ADGS1408/ADGS1409

Data Sheet

Rev. 0 | Page 26 of 34

ROUND ROBIN MODE

Round robin mode allows the ADGS1408/ADGS1409 to cycle

through the channels faster by reducing the overhead needed

from the digital interface to switch from one channel to the next.

The round robin configuration register selects which channels

are to be included in a cycle, and the CNV edge select register

selects on which edge of CNV the ADGS1408/ADGS1409 switch

to the next channel in the sequence. At the end of the channel

cycle, a resync pulse appears on SDO to inform the user that the

current cycle ended; then, SDO loops back to the start of the

sequence of channels. Figure 51 shows an example of the round

robin mode interface, and Figure 52 shows the CNV signal of

the analog-to-digital converter (ADC) being used in conjunction

with the ADGS1408 in round robin mode.

After configuration completes, the round robin enable register

allows the ADGS1408/ADGS1409 to enter round robin mode.

When in round robin mode, the SPI is no longer used to switch

between channels. Instead, to switch from one channel to another,

ensure that a digital signal is present on the CNV pin while CS

is pulled low.

To exit round robin mode, either perform a hardware reset or send

the following two 16-bit addressable mode SPI frames: 0xA318,

followed by 0xE3B4. These frames are the only SPI commands

recognized by the SPI interface while in round robin mode.

Round robin mode is significantly faster than addressable mode

to cycle through channels because it removes the 16-bit overhead

required to change input channel. In addition, round robin mode

removes the need for SCLK to be running, which reduces the

digital current consumption, IL. The maximum CNV frequency

is bound by the transition time of the device along with the

required settling time for the application.

CNV

MUX

CHANNEL

XS1

S(LAST)

ROUND ROBIN CYCLE

SDO

RESYNC

Figure 51. Round Robin Mode Interface Example

CNV

ACQUISITION

tACQ

tCYC

tCONV

tDIS

tEN

CONVERSION

SCK

SDO

MUX

CHANNEL

D15

D14

N + 2

N + 1

D13

AD7980 SDO

SDI

DATA IN

DIGITAL HOST

CLK

VIO

CNV

SCK

CONVERT

IN0

IN1

IN2

IN7

ADGS1408

SCK

GPO

CNV

IN±

Figure 52. Example of the CNV Signal of an ADC Cycling Through Channels in the ADGS1408

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