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ADPD4100 датащи(PDF) 77 Page - Analog Devices

номер детали ADPD4100
подробное описание детали  Multimodal Sensor Front End
PDF  101 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADPD4100 датащи(HTML) 77 Page - Analog Devices

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Data Sheet
ADPD4100/ADPD4101
Rev. 0 | Page 77 of 101
Addr
Name
Bits
Bit Name
Description
Reset Access1
0x0014 INT_ENABLE_XD
15
INTX_EN_FIFO_TH
INT_FIFO_TH interrupt enable. Write a 1 to this bit to
enable drive of the FIFO threshold status on Interrupt X.
0x0
R/W
14
INTX_EN_FIFO_UFLOW INT_FIFO_UFLOW interrupt enable for Interrupt X. Write a
1 to this bit to enable drive of the FIFO underflow status
on Interrupt X.
0x0
R/W
13
INTX_EN_FIFO_OFLOW INT_FIFO_OFLOW interrupt enable for Interrupt X. Write a
1 to this bit to enable drive of the FIFO overflow status on
Interrupt X.
0x0
R/W
12
Reserved
Reserved.
0x0
R
11
INTX_EN_DATA_L
INT_DATA_L interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_L status on Interrupt X.
0x0
R/W
10
INTX_EN_DATA_K
INT_DATA_K interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_K status on Interrupt X.
0x0
R/W
9
INTX_EN_DATA_J
INT_DATA_J interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_J status on Interrupt X.
0x0
R/W
8
INTX_EN_DATA_I
INT_DATA_I interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_I status on Interrupt X.
0x0
R/W
7
INTX_EN_DATA_H
INT_DATA_H interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_H status on Interrupt X.
0x0
R/W
6
INTX_EN_DATA_G
INT_DATA_G interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_G status on Interrupt X.
0x0
R/W
5
INTX_EN_DATA_F
INT_DATA_F interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_F status on Interrupt X.
0x0
R/W
4
INTX_EN_DATA_E
INT_DATA_E interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_E status on Interrupt X.
0x0
R/W
3
INTX_EN_DATA_D
INT_DATA_D interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_D status on Interrupt X.
0x0
R/W
2
INTX_EN_DATA_C
INT_DATA_C interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_C status on Interrupt X.
0x0
R/W
1
INTX_EN_DATA_B
INT_DATA_B interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_B status on Interrupt X.
0x0
R/W
0
INTX_EN_DATA_A
INT_DATA_A interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_A status on Interrupt X.
0x0
R/W
0x0015 INT_ENABLE_YD
15
INTY_EN_FIFO_TH
INT_FIFO_TH interrupt enable. Write a 1 to this bit to
enable drive of the FIFO threshold status on Interrupt Y.
0x0
R/W
14
INTY_EN_FIFO_UFLOW INT_FIFO_UFLOW interrupt enable for Interrupt Y. Write a
1 to this bit to enable drive of the FIFO underflow status
on Interrupt Y.
0x0
R/W
13
INTY_EN_FIFO_OFLOW INT_FIFO_OFLOW interrupt enable for Interrupt Y. Write a
1 to this bit to enable drive of the FIFO overflow status on
Interrupt Y.
0x0
R/W
12
Reserved
Reserved.
0x0
R
11
INTY_EN_DATA_L
INT_DATA_L interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_L status on Interrupt Y.
0x0
R/W
10
INTY_EN_DATA_K
INT_DATA_K interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_K status on Interrupt Y.
0x0
R/W
9
INTY_EN_DATA_J
INT_DATA_J interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_J status on Interrupt Y.
0x0
R/W
8
INTY_EN_DATA_I
INT_DATA_I interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_I status on Interrupt Y.
0x0
R/W
7
INTY_EN_DATA_H
INT_DATA_H interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_H status on Interrupt Y.
0x0
R/W
6
INTY_EN_DATA_G
INT_DATA_G interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_G status on Interrupt Y.
0x0
R/W
5
INTY_EN_DATA_F
INT_DATA_F interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_F status on Interrupt Y.
0x0
R/W
4
INTY_EN_DATA_E
INT_DATA_E interrupt enable. Write a 1 to this bit to
enable drive of INT_DATA_E status on Interrupt Y.
0x0
R/W



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