ADPD4001 datasheet(21/82 Pages) AD

21 / 82 page

Data Sheet

ADPD4000/ADPD4001

Rev. A | Page 21 of 82

Figure 22 shows the basic time slot operation sequence. Each

time slot is repeated at the sampling rate, followed by an ultra

low power sleep period. By default, subsequent time slots are

initiated immediately following the end of the previous time

slot. In addition, there is an option to add an offset to the start

of the subsequent time slots using the TIMESLOT_OFFSET_x

bit field as shown in Figure 23, which shows the TIMESLOT_

OFFSET_B bit field being used to offset the start of Time Slot B.

In this case, each time slot still operates at the sampling rate, but

there is a sleep period between Time Slot A and Time Slot B.

The wake period shown in Figure 22 and Figure 23 is used to

power up and stabilize the analog circuitry before data

acquisition begins. If the TIMESLOT_OFFSET_B bit field is set

to 0, the time slot starts as soon as the previous time slot finishes.

The time slot offset is always applied to the Time Slot A start

time. For example, TIMESLOT_OFFSET_D is an offset added

to the beginning of Time Slot A, not Time Slot C, which

immediately precedes Time Slot D.

The amount of offset applied is dependent on the low frequency

oscillator used. If using the 1 MHz low frequency oscillator,

Offset = 64 × (Number of 1 MHz Low Frequency Oscillator

Cycles) × TIMESLOT_OFFSET_x

If using the 32 kHz low frequency oscillator,

Offset = 2 × (Number of 32 kHz Low Frequency Oscillator

Cycles) × TIMESLOT_OFFSET_x

For example, if TIMESLOT_OFFSET_C is set to 0x040 and the

1 MHz low frequency oscillator is being used, then the offset

from the start of Time Slot A to the start of Time Slot C is

Offset = (64 × 1 µs × 64) = 4.096 ms

The sampling rate is controlled by the low frequency oscillator.

The low frequency oscillator is driven by one of three sources as

described in the Clocking section.

If the sampling period is set too short to allow the enabled time

slots to complete, a full cycle of enabled time slot samples are

skipped, effectively reducing the overall sample rate. For example,

if the sampling rate is set to 100 Hz (10 ms period) and the total

amount of time required to complete all enabled time slots is

11 ms, the next cycle of time slots does not begin until t = 20 ms,

effectively reducing the sampling rate to 50 Hz.

If TIMESLOT_OFFSET_x is set too short to allow the previous

time slot to finish, the time slot occurs immediately after the

previous time slot. Time slots always occur in A through L order.

Using External Synchronization for Sampling

An external signal driven to a configured GPIO pin can be used

to wake from sleep instead of the TIMESLOT_PERIOD_x

counter, which allows external control of the sample rate and time.

This mode of operation is enabled using the EXT_SYNC_EN

bit and uses the GPIO pin selected by the EXT_SYNC_GPIO bit

field. If using this feature, be sure to enable the selected GPIO

pin as an input using the appropriate GPIO_PIN_CFGx bit field.

When operating with external synchronization, the device

enters sleep first when set into go mode and waits for the next

external synchronization signal before waking up. This external

synchronization signal is then synchronized to the low frequency

oscillator and then starts the wake-up sequence. If an additional

external synchronization is provided prior to completing time

slot operations, it is ignored.

EXECUTION MODES

A state machine in the low frequency oscillator clock domain

controls sleep times, wake-up cycles, and the start of time slot

operations. The low frequency oscillator serves as the time base

for all time slot operations, controls the sample rates, and clocks

the low frequency state machine. This state machine controls all

operations and is controlled by the OP_MODE bit.

Table 15. OP_MODE Bit Setting Descriptions

OP_MODE

Setting

Mode

Description

Off

All operations stopped. Time slot actions

reset. Low power standby state.

Transitioning to this state from off mode

starts time slot operation.

At power-up and following any subsequent reset operations, the

ADPD4000/ADPD4001 is in off mode. The user can write 0 to

the OP_MODE bit to immediately stop operations and return

to off mode.

go mode. The user must enter off mode before changing the

control registers. Off mode resets the digital portion of the

ADC, all of the pulse generators, and the state machine.

When OP_MODE is set to 1, the device immediately starts the

first wake-up sequence and time slot operations unless using an

external synchronization trigger. If using an external

synchronization trigger, the device enters the sleep state before

the first wake-up and time slot regions begin.

SLEEP

WAKE

TIME SLOT A

TIME SLOT B

TIME SLOT L

SLEEP

WAKE

TIME SLOT A

TIMESLOT_PERIOD_x/

LOW FREQUENCY OSCILLATOR (s)

Figure 22. Basic Time Slot Operation Sequence

SLEEP

WAKE

TIME SLOT A

SLEEP

WAKE

TIME SLOT B

SLEEP

WAKE

TIME SLOT A

TIMESLOT_PERIOD_x/

LOW FREQUENCY OSCILLATOR (s)

TIME SLOT_OFFSET_B

Figure 23. Time Slot Operation with Offset Using TIMESLOT_OFFSET_x

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