ADPD188GG datasheet(39/61 Pages) AD

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Data Sheet

ADPD188GG

Rev. B | Page 39 of 61

Group

Time Slot A

Time Slot B

Float Mode Description

SLOTx_AFE_WIDTH

0x39,Bits[15:11]

0x3B, Bits[15:11]

Integration time in μs. set to FLT_CONN + 1.

SLOTx_AFE_OFFSET

0x39, Bits[10:0]

0x3B, Bits[10:0]

Integrator start time in 31.25 ns increments. Set to

(SLOTx_LED_OFFSET – SLOTx_AFE_WIDTH − 9.25) μs.

SLOTx_PULSES

0x31, Bits[15:8]

0x36, Bits[15:8]

Number of pulses; must be set in multiples of 2,

minimum 2.

FLT_LED_WIDTH_x

0x3E, Bits[12:8]

0x3F, Bits[12:8]

LED pulse width for float LED mode in μs.

FLT_LED_OFFSET_x

0x3E, Bits[7:0]

0x3F, Bits[7:0]

Time of first LED pulse in float LED mode.

FLT_LED_FIRE_x

0x5A, Bits[11:8]

0x5A, Bits[15:12]

In any given sequence of four pulses, fire the LED in the

selected position. Selections are active low (that is, fire LED

if 0). For example, in a sequence of four pulses on Time Slot B,

Bit 15 is the fourth pulse. For a sequence of four pulses, fire

the LED in the second and third pulses by writing 0x9 to

A timing diagram for a four pulse float LED sequence for

Time Slot B is shown in Figure 40. In this example, the device is

set up for LED pulses of 12 μs that fall within a float period of

16 μs, 2 μs of which are used for dumping of the accumulated

charge on the photodiode. The integration time is set to 3 μs, which

is 1 μs more than the charge dump time to allow for timing margin

when integrating the incoming charge. Note, there is a 9 μs offset

built into the integration start time. Take this offset into account

when setting the SLOTx_AFE_OFFSET value. As shown in

Figure 40, the time of the first charge dump is set to 30 μs. SLOTx_

AFE_OFFSET is set to 0x238 (17.75 μs), taking into account the

3 μs integration time, the 9 μs offset, and an additional 250 ns

for edge placement margin.

To calculate SLOTx_AFE_OFFSET, use the following equation:

SLOTx_AFE_OFFSET = SLOTx_LED_OFFSET –

SLOTx_AFE_WIDTH − 9.25 μs

Placement of the integration period is such that the negative

phase of the integration is centered on the charge dump phase.

The TIA is an inverting stage, therefore, placing the negative

phase of the integration during the dumping of the charge from

the photodiode causes the integrator to increase with the

negative going output signal from the TIA.

The LED flashes in the second and third pulses of the four pulse

sequence. Setting Register 0x58, Bits[6:5] = 2 and Register 0x58,

Bits[11:10] = 1 forces the device to add the second and third

pulses while subtracting the first and fourth pulses, effectively

cancelling out the ambient light and electrical offsets and drift.

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