VR4102 datasheet(64/701 Pages) NEC

64 / 701 page

CHAPTER 2 PIN FUNCTIONS

Table 2-1. System Bus Interface Signals (2/2)

Signal

I/O

Description of function

BUSCLK

This is the system bus clock. It is used to output the clock that is supplied to the controller on the

system bus. Its frequency is determined by the state of the CLKSEL2/TXD, CLKSEL1/RTS#, and

CLKSEL0/DTR pins. (See 2.2.5 RS-232-C Interface Signals.)

SHB#

This is the system bus high-byte enable signal. During system bus access, this signal is active when the

high-order byte is valid on the data bus.

IOR#

This is the system bus I/O read signal. It is active when the VR4102 accesses the system bus to read

data from an I/O port.

IOW#

This is the system bus I/O write signal. It is active when the VR4102 accesses the system bus to write

data to an I/O port.

MEMR#

This is the system bus memory read signal. It is active when the VR4102 accesses the system bus to

read data from memory.

MEMW#

This is the system bus memory write signal. It is active when the VR4102 accesses the system bus to

write data to memory.

ZWS#

This is the system bus zero wait state signal. Set this signal as active to enable the controller on the

system bus to be accessed by the VR4102 without a wait interval.

RSTOUT

This is the system bus reset signal. It is active when the VR4102 resets the system bus controller.

MEMCS16#

This is a dynamic bus sizing request signal.

Set this signal as active when system bus memory accesses data in 16-bit width. (However, the DRAM

bus memory space that is controlled by the DBUS 32 pin is excepted.)

IOCS16#

This is a dynamic bus sizing request signal.

Set this signal as active when system bus I/O accesses data in 16-bit width.

IOCHRDY

This is the system bus ready signal. Set this signal as active when the system bus controller is ready to

be accessed by the VR4102.

HLDRQ#

This is a hold request signal for the system bus and DRAM bus that is sent from an external bus master.

HLDACK#

This is a hold acknowledge signal for the system bus and DRAM bus that is sent to an external bus

master.

DBUS32/

GPIO[48]

I/O

This function differs depending on the operating status.

•

In normal operation (output)

It can be used as a general-purpose output port.

•

After RTC reset (input)

It is a data bus width switching signal.

Sampling occurs when the RTCRST signal changes from low to high.

1 : Use 32-bit width for data bus

0 : Use 16-bit width for data bus

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