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MPC17C724 датащи(PDF) 7 Page - Freescale Semiconductor, Inc |
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MPC17C724 датащи(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 13 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 7 17C724 TIMING DIAGRAMS TIMING DIAGRAMS Figure 4. tPLH and tPHL Timing Figure 5. Low-Voltage Detection Timing Table 5. Truth Table 10% 50% OUTA, OUTB 90% tPLH tPHL IN1, IN2, PSAVE tV DDDET 0% VDD IM 50% tV DDDET 1.0 V 2.5 V VDDDETon VDDDEToff 90% (<1.0 µA) INPUT OUTPUT VDDDET (20) PSAVE(19) IN1A IN2A IN1B IN2B OUT1A OUT2A OUT1B OUT2B LLLLL Enabled L H L H L Enabled L L H L H Enabled L H H Z Z Enabled HX X Z Z Disabled H : High L : Low Z : High impedance X : Don’t care Notes 19. Terminal 13 (PSAVE) is pulled up by an internal resistor. 20. When VDD is lower than VDDDET while VM is applied, output becomes “Z” (high impedance); however, when PSAVE = “H”, the low-voltage shutdown detection circuit is disabled. |
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