10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP5910 is dependant on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5910.

GND pin using as wide and as short of a copper trace as is practical.

Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add

parasitic inductances and resistance that results in inferior performance especially during transient conditions.

10.1.1 DSBGA Mounting

The DSBGA package requires specific mounting techniques, which are detailed in the DSBGA Wafer Level Chip

Scale Package application note. For best results during assembly, alignment ordinals on the PC board may be

used to facilitate placement of the DSBGA device.

10.1.2 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light may cause incorrect operation of the device. High intensity light

sources such as halogen lamps can affect electrical performance if they are situated in close proximity to the

device. The wavelengths that have the most detrimental effect are reds and infra-reds, which means that the

fluorescent lighting used inside most buildings has little effect on performance.

10.2 Layout Examples

C

IN

C

OUT

OUT

IN

GND

EN

A2

B2

A1

B1

Via

Figure 10-1. LP5910 Typical DSBGA Layout

1

2

3

6

5

4

OUT

NC

GND

IN

NC

EN

C

OUT

C

IN

Figure 10-2. LP5910 Typical WSON Layout

LP5910

SNVSA91F – SEPTEMBER 2015 – REVISED APRIL 2021

www.ti.com

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