PCM16C02 datasheet(13/42 Pages) NSC

13 / 42 page

50 Functional Description (Continued)

shall not assert the STSCHG

signal If the PCM16C02 is

not operated as an IO interface this field is undefined and

should be ignored Either Function Configuration Status

if it satis-

fies the above requirements

IOis8

When the host can only provide IO cycles with an

8-bit D0 – D7 path the host shall set this bit to a one (1) The

card is guaranteed that accesses to 16-bit registers will oc-

cur as two byte accesses rather than a single 16-bit access

This information is useful when 16-bit and 8-bit registers

overlap

Audio

Sampling of the signal SPK

IN and control of

SPKR

is accomplished using the Audio bit SPKR

will

equate to SPK

IN anytime either of the Audio bits is set to

one (1) and the function is configured

PwrDn

When the host sets this field to one (1) the

PCM16C02 shall set the given function to a power-down

state by de-asserting the PCNTL( ) signal for that function

While this field is a one (1) the host shall not access the

function on the PC Card The host shall return this field to

zero (0) before attempting to access the function The sys-

tem shall not place the card into a power-down state while

the card’s RDYBSY

line is in the low (Busy) state All

inputoutput

signals

particular

the

function

are

TRI-STATE

Intr

If the function is requesting interrupt servicing (CINT( )

asserted) the PCM16C02 shall set this field to one (1) The

PCM16C02 shall reset this field to zero (0) when the inter-

rupt request has been serviced (CINT( ) de-asserted)

IntrReset

If IntrReset is set to zero (0) Intr shall be set to

one (1) when an interrupt condition occurs and shall be re-

set to zero (0) when the interrupt condition has been serv-

iced A write to the Intr bit will do nothing If IntrReset is set

to one (1) Intr shall be set to one (1) when an interrupt

condition occurs (CINT( ) pin) and be cleared to a zero (0)

when the interrupt (CINT( ) pin) is serviced however a write

of value zero (0) to any FCSR’s Intr bit where IntrReset is

set to one (1) shall cause the PCM16C02 to evaluate all

CINT( ) signals and generate another interrupt to the system

if an interrupt is pending Note that the write of zero (0) to

any FCSR’s Intr bit where IntrReset is set to one (1) is an

indication to the PCM16C02 that it must evaluate all CINT( )

pins and generate a specified pulse to the system on the

IREQ line This protocol will work in either pulse or level

mode (state of aliased LevIREQ controlling IREQ

PC Card

signal mode) Functions operate by asserting their CINT( )

signal when an interrupt condition occurs If interrupts are

enabled for a given function then that function’s CINT( )

pin when asserted may generate an interrupt within the

PCM16C02

National’s PCM16C02 has access to an internal interrupt

line that represents the OR of all interrupts that have been

asserted and enabled Since functions use a level mode

interrupt approach this OR’d internal interrupt signal repre-

sents a level mode ORing of the interrupts When the OR’d

signal is asserted the PCM16C02 will generate either a

pulse mode or level mode interrupt on the IREQ

line Be-

fore EOI processing by the functions ISR the function’s in-

terrupt condition will be cleared and its CINT( ) pin will de-

assert

If no other interrupts are being asserted

the

PCM16C02’s internal line will de-assert IREQ

If other in-

terrupts are pending the internal line remains asserted (and

hence IREQ ) Since the standard PC compatible interrupt

controller requires a positive edge to trigger an interrupt

system software based on using the IntrReset protocol for

the PCM16C02 may write a zero (0) to any Intr bit where

IntrReset is set to one (1) after EOI processing is done This

will cause the PCM16C02 to generate a pulse on the

IREQ

line if any CINT( ) that’s enabled is still asserted In

other words if the internal line is still asserted at this point If

in pulse mode this is a single pulse that goes high-low-high

with at least 05 ms low time If in level mode this pulse is a

low-high-low pulse to trigger the interrupt controller and

then remain low (IREQ

asserted) and be maintained low

by the level mode interrupt This protocol solves both the

need for two positive edges during level mode interrupts

when an interrupt occurs during an interrupt in-service and

solves the need for separate-distinct pulse interrupts that do

not overlap during two interrupt events close in time

Note

For consistency the PCM16C02 will alias all IntrReset bits on a write

to insure that both functions operate in the same mode Also the Intr

bits are aliased on writes as an indicator to the PCM16C02 that inter-

rupt status must be checked and pulses generated per the above

protocol

Function Pin Replacement Registers 01

0x10240x1044

These PC Card registers replace the signals missing from a

PC Card Memory Card interface due to using the PC Card

IO interface

CBVD1 CBVD2 CRdyBsy CWProt RBVD1 RBVD2 RRdyBsy RWProt

CBVD1CBVD2

These bits are not implemented

CRdyBsy

This bit is set to one (1) when RRdyBsy bit

changes state The value of 02h must be written to the Pin

Replacement Registers in order to clear the CRdyBsy bit

CWProt

This bit is not implemented

RBVD1RBVD2RRdyBsyRWProt

Only

RRdyBsy

implemented for each function This bit reflects the state of

the functions READY( ) input pin on the PCM16C02

Function IO Event Registers 01

0x10280x1048

D7–D5

D3–D1

Reserved

RIEvt

Reserved

RIENAB

RIEvt

PCM16C02 latches a one (1) to the Card IO Event

IN( )

pin is asserted for

Function 0 or Function 1 provided the RIEnab bit is set The

value of 10h must be written to the IO Event Register in

order to clear the RIEvt bit (D4)

RIEnab

When this bit is set to a one (1) a latched value of

one (1) on the RIEvt bit shall cause the Changed bit in the

Function’s Configuration Status Register to be set to a one

(1)

Function Base Address Registers 01

0x102A-0x102C0x104A-0x104C

The base address for each function is comprised of 4 bytes

(13 bits implemented) that specify the base IO address

from which to begin decoding for chip selection of a particu-

lar function

Base A Register

D7–D0

Byte 0 (Base Address bits 7–0) of 13-bit Address

This register comprises the low 8 bits of the base address

for the Function IO decode selection

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