LTC3621 datasheet(7/20 Pages) AD

7 / 20 page

LTC3644/LTC3644-2

Rev. 0

For more information www.analog.com

PIN FUNCTIONS

RUN1 (C5): Logic Controlled RUN Input to Channel 1.

Do not leave this pin floating. Logic High activates the

step-down regulator.

RUN2 (F5): Logic Controlled RUN Input to Channel 2.

Do not leave this pin floating. Logic High activates the

step-down regulator.

RUN3 (F2): Logic Controlled RUN Input to Channel 3.

Do not leave this pin floating. Logic High activates the

step-down regulator.

RUN4 (C2): Logic Controlled RUN Input to Channel 4.

Do not leave this pin floating. Logic High activates the

step-down regulator.

SVIN (A5): Signal VIN Pin. This input powers the INTVCC

LDO. May be a different voltage than VIN1, VIN2, VIN3

or VIN4. Connect SVIN to whichever VINX is highest; for

applications where it is not known which VIN is highest,

connect external diode between SVIN to all VINX to ensure

that SVIN is less than a diode drop from the highest VIN.

SW1 (C6): Switch Node Connection to the Inductor of

Channel 1 Step-Down Regulator.

SW2 (D6): Switch Node Connection to the Inductor of

Channel 2 Step-Down Regulator.

SW3 (D1): Switch Node Connection to the Inductor of

Channel 3 Step-Down Regulator.

SW4 (C1): Switch Node Connection to the Inductor of

Channel 4 Step-Down Regulator.

VIN1(B6):InputVoltageofChannel1Step-DownRegulator.

May be a different voltage than other channels’ VIN.

VIN2(E6):InputVoltageofChannel2Step-DownRegulator.

May be a different voltage than other channels’ VIN.

VIN3(E1):InputVoltageofChannel3Step-DownRegulator.

May be a different voltage than other channels’ VIN.

VIN4(B1):InputVoltageofChannel4Step-DownRegulator.

May be a different voltage than other channels’ VIN.

INTVCC (A2): Low Dropout Regulator. Bypass with a low

ESR ceramic cap of at least 4.7µF to ground.

MODE/SYNC (D2): Burst Mode Select and External Clock

Synchronization of the Step-Down Regulator. Tie MODE/

SYNC to INTVCC for Burst Mode operation with a 550mA

peak current clamp. Tie MODE/SYNC to GND for pulse

skipping operation, and tie MODE/SYNC to a voltage

between1VandINTVCC–1.2Vforforcedcontinuousmode.

Furthermore, connecting this pin to an external clock will

synchronize the switch clock to the external clock and put

the part in forced continuous mode.

GND (A3, A4, B3, B4, C3, C4, D3, D4, E3, E4, F3, F4):

Groundbackplaneforpowerandsignalground.Thesepins

must be soldered to PCB ground for electrical contact and

rated thermal performance. Connect all GND pins together

with solid ground plane.

PHASE (D5): Phase Select Pin. Do not leave this pin

floating. Tie this pin to GND to run the regulators in phase

(0 degrees phase shift) between the SW rising edge of

channel 1/2 and channel 3/4. Tie this pin to INTVCC to

set 180 degrees phase shift between channel 1/2 and

channel 3/4. When this pin is high, the phase shift may

also be set by modulating the duty cycle of external clock

on the MODE/SYNC pin (channel 1/2 edge synced to

rising edge of clock, channel 3/4 edge synced to falling

edge of clock). For 5A output configuration, this pin

must be tied to ground. See the Applications Information

section for more details.

PGOOD1 (B5): Open Drain Power Good Indicator for

Channel 1.

PGOOD2 (E5): Open Drain Power Good Indicator for

Channel 2.

PGOOD3 (E2): Open Drain Power Good Indicator for

Channel 3.

PGOOD4 (B2): Open Drain Power Good Indicator for

Channel 4.

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