COP8CFE9 datasheet(13/63 Pages) NSC

13 / 63 page

3.0 Pin Descriptions (Continued)

CKI is the clock input. This can be connected (in conjunction

with CKO) to an external crystal circuit to form a crystal

oscillator. See Oscillator Description section.

RESET is the master reset input. See Reset description

section.

CC is the Analog Supply for A/D converter. It should be

connected to V

CC externally. This is also the top of the

resistor ladder D/A converter used within the A/D converter.

AGND is the ground pin for the A/D converter. It should be

connected to GND externally. This is also the bottom of the

resistor ladder D/A converter used within the A/D converter.

The device contains up to five bidirectional 8-bit I/O ports (A,

B, G, H and L), where each individual bit may be indepen-

dently configured as an input (Schmitt trigger inputs on ports

L and G), output or TRI-STATE under program control. Three

data memory address locations are allocated for each of

these I/O ports. Each I/O port has three associated 8-bit

memory mapped registers, the CONFIGURATION register,

the output DATA register and the Pin input register. (See the

memory map for the various addresses associated with the

I/O ports.)

Figure 3 shows the I/O port configurations. The

DATA and CONFIGURATION registers allow for each port bit

to be individually configured under software control as

shown below:

CONFIGURATION

DATA

Port Set-Up

Hi-Z Input

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

Port A is an 8-bit I/O port. All A pins have Schmitt triggers on

the inputs. The 44-pin package does not have a full 8-bit port

and contains some unbonded, floating pads internally on the

chip. The binary value read from these bits is undetermined.

The application software should mask out these unknown

bits when reading the Port A register, or use only bit-access

program instructions when accessing Port A. These uncon-

nected bits draw power only when they are addressed (i.e.,

in brief spikes). Additionally, if Port A is being used with some

combination of digital inputs and analog inputs, the analog

inputs will read as undetermined values and should be

masked out by software.

Port A supports the analog inputs for the A/D converter. Port

A has the following alternate pin functions:

A7 Analog Channel 7

A6 Analog Channel 6

A5 Analog Channel 5

A4 Analog Channel 4

A3 Analog Channel 3

A2 Analog Channel 2

A1 Analog Channel 1

A0 Analog Channel 0

Port B is an 8-bit I/O port. All B pins have Schmitt triggers on

the inputs. If Port B is being used with some combination of

digital inputs and analog inputs, the analog inputs will read

as undetermined values. The application software should

mask out these unknown bits when reading the Port B

accessing Port B.

Port B supports the analog inputs for the A/D converter. Port

B has the following alternate pin functions:

B7 Analog Channel 15 or A/D Input

B6 Analog Channel 14 or Analog Multiplexor Output

B5 Analog Channel 13 or Analog Multiplexor Output

B4 Analog Channel 12

B3 Analog Channel 11

B2 Analog Channel 10

B1 Analog Channel 9

B0 Analog Channel 8

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O

ports. Pin G6 is always a general purpose Hi-Z input. All pins

have Schmitt Triggers on their inputs. Pin G1 serves as the

dedicated WATCHDOG output with weak pull-up if the

WATCHDOG feature is selected by the Option register.

The pin is a general purpose I/O if WATCHDOG feature is

not selected. If WATCHDOG feature is selected, bit 1 of the

Port G configuration and data register does not have any

effect on Pin G1 setup. G7 serves as the dedicated output

pin for the CKO clock output.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin, the associated bits in the data and configu-

ration registers for G6 and G7 are used for special purpose

functions as outlined below. Reading the G6 and G7 data

bits will return zeros.

The device will be placed in the HALT mode by writing a “1”

to bit 7 of the Port G Data Register. Similarly the device will

be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register

enables the MICROWIRE/PLUS to operate with the alter-

nate phase of the SK clock. The G7 configuration bit, if set

high, enables the clock start up delay after HALT when the

R/C clock configuration is used.

Config. Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

G7 CKO Oscillator dedicated output

G6 SI (MICROWIRE/PLUS Serial Data Input)

G5 SK (MICROWIRE/PLUS Serial Clock)

G4 SO (MICROWIRE/PLUS Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G1 WDOUT WATCHDOG and/or Clock Monitor if WATCH-

DOG enabled, otherwise it is a general purpose I/O

G0 INTR (External Interrupt Input)

G0 through G3 are also used for In-System Emulation.

Port H is an 8-bit I/O port. All H pins have Schmitt triggers on

the inputs.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on

the inputs.

Port L supports the Multi-Input Wake-up feature on all eight

pins. Port L has the following alternate pin functions:

L7 Multi-Input Wake-up

L6 Multi-Input Wake-up

L5 Multi-Input Wake-up or T2B (Timer T2B Input)

L4 Multi-input Wake-up or T2A (Timer T2A Input)

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