ZL30791, ZL30795, ZL30793

Product Brief

3

Microsemi Confidential

3. Detailed Features

3.1

Input Block Features

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Ten input reference pins; each can accept a CMOS signal or the POS side of a differential pair; or two

can be paired to accept both sides of a differential pair

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Any input can be a SYNC signal for REF+SYNC frequency/phase/time locking

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Any input can be a clock signal with embedded PPS signal (duty cycle distortion indicates PPS location)

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Input clocks can be any frequency from 0.5Hz up to 900MHz (180MHz max for CMOS inputs)

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Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless

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Inputs constantly monitored by programmable frequency and single-cycle monitors

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Single-cycle monitor can quickly disqualify a reference when measured period is incorrect

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Frequency measurement (ppb or Hz) and monitoring (coarse, fine, and frequency-step monitors)

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Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs

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Input-to-input phase measurement, 1ps resolution

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Input-to-DPLL phase measurement, 1ps resolution

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Per-input phase adjustment, 1ps resolution

3.2

DPLL Features

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One, two or three full-featured DPLLs

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Very high-resolution DPLL architecture

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State machine automatically transitions among freerun, tracking and holdover states

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Revertive or nonrevertive reference selection algorithm

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Programmable bandwidth from 0.1mHz to 470Hz

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Less than 0.1dB gain peaking

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Fast frequency/phase/time lock capability for 1PPS or clock+1PPS input references

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Programmable phase-slope limiting (PSL)

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Programmable frequency rate-of-change limiting (FCL)

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Programmable tracking range (i.e. hold-in range)

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Truly hitless reference switching and mode switching

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Physical-to-physical reference switching

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Physical-to-packet reference switching

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Packet-to-physical reference switching

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Packet-to-packet reference switching

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Per-DPLL phase adjustment, 1ps resolution

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High-resolution frequency and phase measurement

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Fast detection of input clock failure and transition to holdover mode

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High-resolution holdover frequency averaging, better than 0.01ppb when using <10mHz filter

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Time-of-Day registers: 48-bit seconds, 32-bit nanoseconds, writeable on input PPS edge

3.3

Synthesizer Features

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Any-to-any frequency conversion with 0ppm error

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Two low-jitter synthesizers (Synth1, Synth2) with very high-resolution fractional scaling (i.e. non-integer

multiplication)

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Two output dividers per low-jitter synthesizer: one integer (4 to 15 plus half divides 4.5 to 7.5) and one

40-bit fractional

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One general-purpose synthesizer (Synth0)

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A total of five output frequency families

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Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter

components

3.4

Low-Jitter Output Clock Features

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Up to 16 single-ended outputs (up to 8 differential outputs) from Synth1 and Synth2

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Each output can be one differential output or two CMOS outputs

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Output clocks can be any frequency from 1Hz to 1045MHz (250MHz max for CMOS and HSTL outputs)