MCP47FXBX4 datasheet(53/124 Pages) MICROCHIP

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DS20006368A-page 53

MCP47FXBX4/8

4.0

GENERAL DESCRIPTION

The MCP47FXBX4 (MCP47FXB04, MCP47FXB14,

and MCP47FXB24) devices are quad-channel voltage

output devices. The MCP47FXBX8 (MCP47FXB08,

MCP47FXB18 and MCP47FXB28) devices are octal-

channel voltage output devices.

These devices are offered with 8-bit (MCP47FXB0X),

10-bit (MCP47FXB1X) and 12-bit (MCP47FXB2X) res-

olutions and include nonvolatile memory (EEPROM),

an I2C serial interface and two write Latch pins (LAT0,

LAT1) to control the update of the written DAC value to

the DAC output pin.

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software-

selectable voltage reference source. The source can

be either the device’s internal VDD, an external VREF

pin voltage (buffered or unbuffered), or an internal

band gap voltage source.

The DAC output is buffered with a low power and

precision output amplifier (op amp). This output

amplifier provides a rail-to-rail output with low offset

voltage and low noise. The gain (1x or 2x) of the out-

put buffer is software configurable.

This device family also has user-programmable non-

volatile memory (EEPROM) option, which allows the

user to save the desired POR/BOR value of the DAC

High-voltage lock bits can be used to ensure that the

device’s output settings are not accidentally modified.

The device operates from a single-supply voltage. This

voltage is specified from 2.7V to 5.5V for full specified

operation, and from 1.8V to 5.5V for digital operation.

The device can operate between 1.8V and 2.7V, but its

analog performance is significantly reduced; therefore,

most device parameters are not specified for this

range.

The main functional blocks are:

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• Resistor Ladder

• Output Buffer/VOUT Operation

• Internal Band Gap

•I2C Serial Interface Module

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

The internal POR/BOR circuit monitors the power

supply voltage (VDD) during operation. This circuit

ensures correct device start-up at system power-up

and power-down events. The device’s RAM retention

voltage (VRAM) is lower than the POR/BOR voltage trip

point (VPOR/VBOR). The maximum VPOR/VBOR voltage

is less than 1.8V.

POR occurs as the voltage rises (typically from 0V),

while BOR occurs as the voltage falls (typically from

VDD(MIN) or higher).

The POR and BOR trip points are at the same voltage and

the condition is determined by whether the VDD voltage is

rising or falling (see Figure 4-1). What occurs is different

depending on whether the reset is a POR or BOR.

When

VPOR/VBOR <VDD < 2.7V,

the

electrical

performance

may

not

meet

the

data

sheet

specifications. In this region, the device is capable of

reading and writing to its EEPROM and reading and

writing to its volatile memory if the proper serial

command is executed.

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