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3.3V 125-MHz Multi-Output Zero Delay Buffer
CY29973
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07291 Rev. *B
Revised January 19, 2004
Features
• Output Frequency up to 125 MHz
• 12 Clock Outputs: Frequency Configurable
• 350-ps max. Output to Output Skew
• Configurable Output Disable
• Two Reference Clock Inputs for Dynamic Toggling
• Oscillator or PECL Reference Input
• Spread Spectrum Compatible
• Glitch-free Output Clocks Transitioning
• 3.3V Power Supply
• Pin Compatible with MPC973
• Industrial Temp. Rang: –40°C to +85°C
• 52-Pin TQFP Package
Note:
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
Table 1. Frequency Table[1]
VC0_SEL FB_SEL2
FB_SEL1
FB_SEL0
FVC0
0000
8x
0001
12x
0010
16x
0011
20x
0100
16x
0101
24x
0110
32x
0111
40x
1000
4x
1001
6x
1010
8x
1011
10x
1100
8x
1101
12x
1110
16x
1111
20x
Block Diagram
Pin Configuration
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
PECL_CLK
PECL_CLK#
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
CY29973
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