916.50 MHz

Receiver Module

RF Monolithics, Inc.

Phone: (972) 233-2903

Fax: (972) 387-8148

E-mail: info@rfm.com

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RFM Europe

Phone: 44 1963 251383

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http://www.rfm.com

©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.

DR5000-081203

Data Out

3 Vdc

2.4 kbps Application Circuit

1

2

3

4

5

8

9

10

11

12

13

14

DR3000

7

6

DR5000

Data Out

3 Vdc

19.2 kbps Application Circuit

1

2

3

4

5

8

9

10

11

12

13

14

7

6

33 k

DR5000

8

LPF ADJ

This pin is the receiver low-pass filter bandwidth adjust, and is connected directly to the receiver LPFADJ pin. R6 on the cir-

cuit board (330 K) is connected between LPFADJ and ground will be in parallel with any external resistor connected to LPF

ADJ. The filter bandwidth is set by the parallel resistance of R6 and the external resistor (if used). The equivalent resistor

bandwidth is determined by:

with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response.

The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. As shipped, the

receiver module is set up for nominal 2.4 kbps operation. An external resistor can be added between Pin 8 and ground to

support higher data rates. Preamble training times will not be decreased, however, unless C3 is replaced with a smaller

capacitor value (see the descriptions of Pins 2 and 3 above). Refer to sections 1.4.3, 2.5.1 and 2.6.1 in the ASH Transceiver

Designer's Guide for additional information on data rate adjustments.

9

VCC

This is the positive supply voltage pin for the module. The operating voltage range is 2.7 to 3.5 Vdc. It is also possible to use

Pin 1 as the Vcc input. Please refer to the Pin 1 description above.

10

GND

This is the supply voltage return pin.

11

CTR1

CTR1 is connected to the CNTRL1 control pin on the receiver. CTR1 and CTR0 select the transceiver operating modes.

CTR1 and CTR0 both high place the unit in the receive mode. CTR1 and CTR0 both low place the unit in the power-down

(sleep) mode. CTR1 is a high-impedance input (CMOS compatible). This pin must be held at a logic level; it cannot be left

unconnected. At turn on, the voltage on this pin and CTR0 should rise with VCC until VCC reaches 2.7 Vdc (receive mode).

Thereafter, any mode can be selected.

12

CTR0

CTR0 is connected to the CNTRL0 control pin on the receiver CTR0 is used with CTR1 to control the operating modes of the

receiver. CTR0 is a high-impedance input (CMOS compatible). This pin must be held at a logic level; it cannot be left uncon-

nected. At turn on, the voltage on this pin and CTR1 should rise with VCC until VCC reaches 2.7 Vdc (receive mode). There-

after, any mode can be selected.

13

RFIO

RFIO is the RF input/output pin. A matching circuit for a 50 ohm load (antenna) is implemented on the circuit board between

this pin and the receiver SAW filter transducer.

14

RF GND

This pin is the RF ground (return) to be used in conjunction with the RFIO pin. For example, when connecting the transceiver

module to an external antenna, the coaxial cable ground is connected this pin and the coaxial cable center conductor is con-

nected to RFIO.