VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC830

Dual 2x2 Crosspoint Switch

2.7Gb/s Asynchronous

G52192-0, Rev 4.0

Page 17

05/23/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

High-Speed Serial I/O Layout Considerations

The high-speed serial signals contain digital data at fundamental frequencies up to 2.488GHz clock rate.

Given that, in order to preserve the edges of such data sequences, it is necessary to have excellent frequency and

the reader follow the general design rules below:

1.

Keep traces as short as possible. Initial component placement should be very carefully considered.

2.

The impedance of the traces must match that of the terminations, connectors and cable(s) in order to reduce

reflections and impedance mismatches. Reflections can create standing waves that will increase the signal

jitter.

3.

Differential transmission line impedance must be maintained at 100

Ω.

4.

When routing differential pairs, keep the lengths identical for both traces. Differences in trace length trans-

late directly into signal skew and can add to the signal jitter. Remember also that the differential impedance

is affected by the separation between the traces.

5.

Keep differential pair traces on the same side of the PCB to minimize impedance discontinuity, such as the

one caused when using printed-circuit board vias.

6.

Eliminate or reduce stubs.

7.

Use rounded corners rather than 45

° or 90° corners.

8.

Keep signal traces far from other signals which might capacitively couple noise into the signals. This

includes the other trace of a differential pair or the traces of the parallel PECL or TTL interface.

9.

Do not cut up the power or ground planes in an effort to steer current paths. This usually produces more

noise, not less.