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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT83036 датащи(PDF) 16 Page - Holtek Semiconductor Inc |
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HT83036 датащи(HTML) 16 Page - Holtek Semiconductor Inc |
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16 / 21 page  HT83XXX Rev. 0.10 16 August 25, 2003 Preliminary The TMR0C is the timer counter 0 control register, which defines the timer counter 0 options. The timer counter 1 has the same options as the timer counter 0 and is de- fined by TMR1C. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. The overflow of the timer counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. The TMR0/1 is internal clock source only. There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which de- fines different division ratio of TMR0/1 ¢s clock source. Time Base The time base enables the counting operation by INTC.1 (ETBI) bit. The overflow to interrupt as set INTC.1. The time base is internal clock source only. Time base of 1ms to overflow as system clock is 4MHz. Time base of 0.5ms to overflow as system clock is 8MHz. S y s t e m C l o c k 8 - S t a g e P r e s c a l e r T i m e r C o u n t e r 0 / 1 P r e l o a d R e g i s t e r D a t a B u s R e l o a d O v e r f l o w t o I n t e r r u p t T i m e r C o u n t e r 0 / 1 T O N ( T M R S 2 , T M R S 1 , T M R S 0 ) Timer Counter 0/1 ¸ 1 0 2 4 S y s t e m C l o c k / 4 O v e r f l o w t o I n t e r r u p t Time Base The registers states are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT) PC 0000H 0000H 0000H 0000H 0000H MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu TMR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR0C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- TMR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- LATCH0H ---- --xx ---- --uu ---- --uu ---- --uu ---- --uu LATCH0M xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu LATCH0L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PWMCR -00- 00-0 -uu- uu-u -uu- uu-u -uu- uu-u -uu- uu-u PWMD xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu LATCHD xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Note: ²u² means ²unchanged²; ²x² means ²unknown²; ²-² means ²undefined² |
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