PRT2011CVL4A datasheet(72/113 Pages) NXP

72 / 113 page

i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020

NXP Semiconductors

Electrical Characteristics

4.9.3.2

eMMC4.4/4.41 (dual data rate) AC timing

Figure 44 depicts the timing of eMMC4.4/4.41. Table 61 lists the eMMC4.4/4.41 timing characteristics.

Be aware that only DATA is sampled on both edges of the clock (not applicable to CMD).

Table 60. SD/eMMC4.3 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP1

1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP2

2 In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0

–25 MHz. In high-speed mode,

clock frequency can be any value between 0

–50 MHz.

25/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP3

3 In normal (full) speed mode for MMC card, clock frequency can be any value between 0

–20 MHz. In high-speed mode, clock

frequency can be any value between 0

–52 MHz.

20/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

7—

SD3

Clock High Time

tWH

7—

SD4

Clock Rise Time

tTLH

—3

SD5

Clock Fall Time

tTHL

—3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6

uSDHC Output Delay

tOD

-6.6

3.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7

uSDHC Input Setup Time

tISU

2.5

—

SD8

uSDHC Input Hold Time4

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

tIH

1.5

—

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