Philips Semiconductors

Preliminary specification

80C453/83C453/87C453

CMOS single-chip 8-bit microcontrollers

1996 Aug 15

3-316

IE.0

IE.2

INT0

IT0

TF0

INT1

IT1

TF1

RI

TI

IE REGISTER

IP REGISTER

HIGH PRIORITY

INTERRUPT

INTERRUPT

POLLING

SEQUENCE

LOW PRIORITY

INTERRUPT

INDIVIDUAL

ENABLES

GLOBAL

DISABLE

0

1

0

1

IBF

SU00562

IE.1

IE.3

IE.4

IE.5

OBF

IE.6

Figure 1. 8XC453 Interrupt Control System

EX0

LSB

MSB

BIT

SYMBOL

FUNCTION

IE.7

EA

Disables all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt

source is individually enabled or disabled by setting or clearing its enable bit.

IE.6

IOB

Enables or disables the Output Buffer Full (OBF) interrupt. If IOB=0, the interrupt is disabled,

If IOB=1, an interrupt will occur if EA is set and data has been read from the output buffer

register through Port 6 by the external host pulsing ODS low.

IE.5

IIB

Enables or disables the Input Buffer Full (IBF) interrupt. If IIB=0, the interrupt is disabled. If

IIB=1, an interrupt will occur if EA is set and data has been written into the Port 6 Input Data

Buffer by the host strobing IDS low.

IE.4

ES

Enables or disables the Serial Port Interrupt. If ES=0, the Serial Port Interrupt. If ES=0, the

Serial Port interrupt is disabled.

IE.3

ET1

Enables or disables the Timer 1 Overflow interrupt. If ET1=0, the Timer 1 interrupt is disabled.

IE.2

EX1

Enables or disables External Interrupt 1. If EX1=0, External Interrupt 1 is disabled.

IE.1

ET0

Enables or disables the Timer 0 Overflow interrupt. If ET0=0, the Timer 0 interrupt is disabled.

IE.0

EX0

Enables or disables External Interrupt 0. If EX0=0, external Interrupt 0 is disabled.

SU00563

ET0

EX1

ET1

ES

IIB

IOB

EA

Figure 2. 8XC453 Interrupt Enable (IE) Register