P80CL31HFP datasheet(21/40 Pages) PHILIPS

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Philips Semiconductors

Product specification

80CL31/80CL51

Low-voltage single-chip 8-bit microcontrollers

January 1995

Interrupt polarity register IX1

IX1 (E9H)

IL9

IL8

IL7

IL6

IL5

IL4

IL3

IL2

Bit

Symbol

Function

IX1.7

IL9

External interrupt 9 polarity level

IX1.6

IL8

External interrupt 8 polarity level

IX1.5

IL7

External interrupt 7 polarity level

IX1.4

IL6

External interrupt 6 polarity level

IX1.3

IL5

External interrupt 5 polarity level

IX1.2

IL4

External interrupt 4 polarity level

IX1.1

IL3

External interrupt 3 polarity level

IX1.0

IL2

External interrupt 2 polarity level

Interrupt request flag register IRQ1

IRQ1 (C0H)

IQ9

IQ8

IQ7

IQ6

IQ5

IQ4

IQ3

IQ2

Bit

Symbol

Function

IRQ1.7 IQ9 External interrupt 9 request flag

IRQ1.6 IQ8 External interrupt 8 request flag

IRQ1.5 IQ7 External interrupt 7 request flag

IRQ1.4 IQ6 External interrupt 6 request flag

IRQ1.3 IQ5 External interrupt 5 request flag

IRQ1.2 IQ4 External interrupt 4 request flag

IRQ1.1 IQ3 External interrupt 3 request flag

IRQ1.0 IQ2 External interrupt 2 request flag

1.6.2

Interrupt Vectors

Vector

Source

0003H

External 0

0023H

UART SIO

0053H

External 5

000BH

Timer 0

005BH

External 6

0013H

External 1

003BH

External 2

0063H

External 7

001BH

Timer 1

0043H

External 3

006BH

External 8

004BH

External 4

0073H

External 9

Interrupt priority

Each interrupt priority source can be set to either high or low priority.

If both priorities are requested simultaneously, the controller will

branch to the high priority vector.

A low priority interrupt can only be interrupted by a high priority

interrupt. A high priority interrupt routine cannot be interrupted.

1.6.3

Related registers

The following registers are used in conjunction with the interrupt

system:

Function

IX1

Interrupt polarity register

IRQ1 Interrupt enable register

IEN1 Interrupt enable register (INT2-INT9)

IP0

Interrupt priority register

IP1

Interrupt priority register (INT2-INT9)

1.7

Oscillator registers

The on-chip circuitry of the 80CL51 is a single-stage inverting

amplifier biased by an internal feedback resistor (Figure 13). For

operation as standard quartz oscillator, no external components are

needed except at 32 KHz. When using external capacitors, ceramic

resonators, coils and RC networks to drive the oscillator, five

different configurations are supported (see Figure 14 and oscillator

options).

In the Power-down mode the oscillator is stopped XTAL1 is pulled

HIGH. The oscillator inverter is switched off to ensure no current will

flow regardless of the voltage at XTAL1. To drive the device with an

external clock source, apply the external clock signal to XTAL1, and

leave XTAL2 to float, as shown in Figure 14(f). There are no

requirements on the duty cycle of the external clock, since the input

to the internal clocking circuitry is split sing a flip-flop.

The following options are provided for optimum on-chip oscillator

performance. Please state option when ordering

1.7.1

Oscillator options (see Figure 14)

The following options are provided for optimum on-chip oscillator

performance. Please state option when ordering.

Osc.1:

Figure 14(c): An option for 32 kHz clock applications with

external trimmer for frequency adjustment. A 4.7 MQ bias

resistor is needed for use in parallel with the crystal.

Osc. 2: Figure 14(e): An option for low-power, low-frequency

operations using LC components.

Osc. 3: An option for medium frequency range applications.

Osc. 4: An option for high frequency range applications.

RC:

Figure 14(g): An option for an RC oscillator.

Figure 13. Oscillator

80CL51

VDD

C1i

Rbias

VDD

TO INTERNAL

TIMING CIRCUITS

VDD

C2i

XTAL1

XTAL2

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