______________________________________________________________________________________________________________________________________________

DSC2021

Page 2

MK-Q-B-P-D-12042604-2

DSC2021

Low-Jitter Configurable Dual LVPECL-CMOS Oscillator

Pin Description

Pin No.

Pin Name

Pin

Type

Description

1

Enable

I

Enables outputs when high and disables (tri-state) them when low

2

NC

NA

Leave unconnected or grounded

3

OS0

I

Least significant bit for output drive strength selection for CMOS

4

GND

Power

Ground

5

FS0

I

Least significant bit for frequency selection

6

FS1

I

Middle bit for frequency selection

7

FS2

I

Most significant bit for frequency selection

8

Output1+

O

Positive LVPECL Output 1

9

Output1-

O

Negative LVPECL Output 1

10

OS1

I

Middle bit for output drive strength selection for CMOS

11

Output 2

O

CMOS output

12

VDD2

Power

Power Supply 2 for CMOS Output

13

VDD

Power

Power Supply

14

OS2

I

Most significant bit for output drive strength selection for CMOS

Operational Description

The DSC2021 is a dual output LVPECL-CMOS

oscillator consisting of a MEMS resonator and

a support PLL IC. The two outputs, CMOS and

LVPECL, are generated through independent

8-bit programmable dividers from the output

of the internal PLL. Two constraints are

1.7GHz.

The actual frequencies output by the DSC2021

are controlled by an internal pre-programmed

memory (OTP).

This memory stores all

coefficients required by the PLL for up to eight

different frequency combinations.

Three

control pins (FS0 – FS2) select the output

frequency combination.

Discera supports

customer defined versions of the DSC2021.

Standard frequency options are described in in

the following sections.

The DSC2021 provides control of the output

voltage levels of the CMOS output. VDD2 (pin

12) sets the high voltage level of Output 2 and

must be equal to or less than VDD at all times

to insure proper operation. VDD2 can be as

low as 1.65V.

When Enable (pin 1) is floated or connected to

VDD, the DSC2021 is in operational mode.

Driving Enable to ground will tri-state both

output drivers (hi-impedance mode).

The DSC2021 has programmable output drive

strength for CMOS output. Using three control

pins (OS0-OS2), the drive strength for CMOS

output (output 2) can be adjusted to match

circuit board impedances to reduce power

supply noise, overshoot/undershoot and EMI.

Table 1 displays typical rise / fall times for the

output with a 15pf load capacitance as a

function of these control pins at VDD=3.3V

and room temperature.

Table 1. Rise/Fall times for drive strengths

Output Drive Strength Bits

[OS2, OS1, OS0] - Default [111]

000 001 010 011 100 101 110 111

2

1.8 1.6 1.3 1.3