Failsafe™ 2.5V/ 3.3V Zero Delay Buffer
CY23FS08
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07518 Rev. *A
Revised May 12, 2004
Features
• Internal DCXO for continuous glitch-free operation
• Zero input-output propagation delay
• Low jitter (< 35 ps RMS) outputs
• Low output-output skew (< 200 ps)
• 1 MHz–200 MHz reference input
• Supports industry standard input crystals
• 200 MHz (commercial), 166 MHz (industrial) outputs
• 5V-tolerant inputs
• Phase-locked loop (PLL) Bypass Mode
• Dual Reference Inputs
• 28-pin SSOP
• Split 2.5V or 3.3V output power supplies
• 3.3V core power supply
• Industrial temperature available
Functional Description
The CY23FS08 is a FailSafe™ Zero Delay Buffer with two
reference clock inputs and eight phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
Continuous, glitch-free operation is achieved by using a
DCXO, which serves as a redundant clock source in the event
of a reference clock failure by maintaining the last frequency
and phase information of the reference clock.
The unique feature of the CY23FS08 is that the DCXO is in
fact the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically resynchro-
nizes to the external clock.
The frequency of the crystal, which will be connected to the
DCXO must be chosen to be an integer factor of the frequency
of the reference clock. This factor is set by four select lines:
S[4:1]. please see Table 1. The CY23FS08 has three split
power supplies; one for core, another for Bank A outputs and
the third for Bank B outputs. Each output power supply, except
VDDC can be connected to either 2.5V or 3.3V. VDDC is the
power supply pin for internal circuits and must be connected
to 3.3V.
Block Diagram
Pin Configuration
CLKA[1:4]
CLKB[1:4]
DCXO
Decoder
4
FailsafeTM
Block
PLL
XIN XOUT
4
4
REF2
FBK
S[4:1]
FAIL# /SAFE
REF1
REFSEL
CLKB1
S2
S3
VDDB
CLKB2
S4
VDDB
XIN
VDDC
FAIL#/SAFE
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
28 pin SSOP
REF1
REF2
VSSB
REFSEL
FBK
VSSA
CLKA1
CLKA2
S1
VDDA
9
10
11
12
13
14
VSSB
CLKB3
CLKB4
20
19
18
17
16
15
VSSA
CLKA3
CLKA4
VDDA
XOUT
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