CY7C1001
CY7C1002
PRELIMINARY
3
AC Test Loads and Waveforms
C1001-3
C1001-4
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 3 ns
< 3 ns
OUTPUT
R1 480W
R1 480W
R2
255W
R2
255W
167W
Equivalent to:
THÉVENIN EQUIVALENT
1.73V
Switching Characteristics Over the Operating Range[3, 6]
7C1001-12
7C1002-12
7C1001-15
7C1002-15
7C1001-20
7C1002-20
7C1001-25
7C1002-25
Parameter
Description
Min.
Max.
Min.
Max.
Min. Max.
Min. Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
15
20
25
ns
tAA
Address to Data Valid
12
15
20
25
ns
tOHA
Data Hold from Address Change
3
3
3
3
ns
tACE
CE LOW to Data Valid
12
15
20
25
ns
tLZCE
CE LOW to Low Z[7]
3
3
3
3
ns
tHZCE
CE HIGH to High Z[7, 8]
6
7
8
10
ns
tPU
CE LOW to PowerUp
0
0
0
0
ns
tPD
CE HIGH to PowerDown
12
15
20
25
ns
WRITE CYCLE[9]
tWC
Write Cycle Time
12
15
20
25
ns
tSCE
CE LOW to Write End
10
12
15
20
ns
tAW
Address SetUp to Write End
10
12
15
20
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address SetUp to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
10
12
15
20
ns
tSD
Data SetUp to Write End
7
8
10
15
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
3
3
ns
tHZWE
WE LOW to High Z[7, 8]
6
7
8
10
ns
tDWE
WE LOW to Data Valid (7C1001)
12
15
20
25
ns
tDCE
CE LOW to Data Valid (7C1001)
12
15
20
25
ns
tADV
Data Valid to Output Valid (7C1001)
12
15
20
25
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing ref
erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOL/IOH and 30pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than
tLZCE and tHZWE is less than tLZWE for any given device.
8. tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in
part (b) of AC Test Loads. Transition is measured ±500 mV from
steadystate voltage.
9. The internal write time of the memory is defined by the overlap of CE
and WE LOW. CE and WE must be LOW to initiate a write, and the
transition of any of these signals can terminate the write. The input
data setup and hold timing should be referenced to the leading edge
of the signal that terminates the write.
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
