MC56F81663VLC datasheet(8/73 Pages) NXP

8 / 73 page

1.5.6 Periodic Interrupt Timer (PIT) Modules

• 32-bit counter with programmable count modulo

• PIT0 is master and PIT1 is slave (if synchronizing both PITs)

• The output signals of both PIT0 and PIT1 are internally connected to a peripheral

crossbar module

• Can run when the CPU is in Wait/Stop modes. Can also wake up the CPU from

Wait/Stop modes.

• In addition to its existing bus clock (up to 50 MHz), 3 alternate clock sources for the

counter clock are available:

• Crystal oscillator output

• 8 MHz / 2 MHz internal RC output

• On-chip low-power 200 kHz oscillator

1.5.7 Quadrature Decoder (QDC)

• Includes logic to decode quadrature signals

• Inputs can be connected to a general purpose timer to make low speed velocity

measurements

• Configurable digital filter for inputs

• Quadrature decoder filter can be bypassed

• 32-bit position counter capable of modulo counting

• Position counter can be initialized by software or external events

• 16-bit position difference register

• Compare function can indicate when shaft has reached a defined position

• A watchdog timer can detect a non-rotating shaft condition

• Preloadable 16-bit revolution counter

• Maximum count frequency equals the peripheral clock rate

• Optional interrupt when both PHASEA and PHASEB inputs change in the same

cycle

1.5.8 Inter-Module Crossbar and Event Generator (EVTG) logic

• Provides generalized connections between and among on-chip peripherals: ADCs,

12-bit DAC, comparators, quad-timers, eFlexPWMs, EWM, quadrature decoder, and

select I/O pins

• User-defined input/output pins for all modules connected to the crossbar

• DMA request and interrupt generation from the crossbar

Peripheral highlights

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663VLC датащи(PDF) 8 Page - NXP Semiconductors