∆ IP−P

8 × ∆ VQ × fSW

where:

(VIN − VOUT) × VOUT

VIN × fSW × L

and:

allowable deviation of the output voltage during fast transient loads also determines the output capacitance and its ESR.

The output capacitor supplies the step-load current until the converter responds with a greater duty cycle. The resistive

drop across the output capacitor’s ESR and the capacitor discharge causes a voltage droop during a step load. Use a

combination of low-ESR tantalum and ceramic capacitors for better transient-load and ripple/noise performance. Keep

the maximum output-voltage deviations below the tolerable limits of the electronics being powered. When using a ceramic

capacitor, assume an 80% and 20% contribution from the output-capacitance discharge and the ESR drop, respectively.

Use the following equations to calculate the required ESR and capacitance value:

Equation 3:

∆ VESR

ISTEP

L

2 × (VSUP − VOUT) × DMAX × ∆ VQ

tDELAY

∆ VQ

the load step occurs right after a turn-on cycle. This delay is higher in skip mode.

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching power losses and clean, stable operation. Use a multilayer board

whenever possible for better noise immunity. Follow the guidelines below for a good PCB layout:

formed by the input capacitor and the half-bridge MOSFETs internal to the device (see Figure 2). A small loop would

reduce the radiating effect of high switching currents and improve EMI functionality.

2. Solder the exposed pad to a large copper-plane area under the device. To effectively use this copper area as heat

exchanger between the PCB and ambient, expose the copper area on the top and bottom side. Add a few small vias

or one large via on the copper pad for efficient heat transfer.

3. Connect PGND and AGND pins directly to the exposed pad under the IC. This ensures the shortest connection path

between AGND and PGND.

4. Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper

PCB to enhance full-load efficiency and power-dissipation capability.

5. Using internal PCB layers as ground plane helps to improve the EMI functionality as ground planes act as a shield

against radiated noise. Have multiple vias spread around the board, especially near the ground connections to have

better overall ground connection.

bias for smoother operation.

MAX25232

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