2013. 12. 10

3/4

Revision No : 0

FTV05LUT

IEC 61000−4−2 Spec.

Level

Test

Voltage

(kV)

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

1

2

7.5

4

2

2

4

15

8

4

3

6

22.5

12

6

4

8

30

16

8

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

Figure 3. IEC61000−4−2 Spec

Figure 4. Diagram of ESD Test Setup

50

50

Cable

TVS

Oscilloscope

ESD Gun

The following is taken from Application Note

AND8308/D −Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000-4-2 waveform. Since the

IEC61000-4-2 2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

Figure 5. 8 X 20 s Pulse Waveform

100

90

80

70

60

50

40

30

20

10

0

0

20

40

60

80

t, TIME ( s)

AS THAT POINT WHERE THE

PEAK CURRENT DECAY = 8us