PCI1520PDVG4 datasheet(25/140 Pages) TI

25 / 140 page

2−12

Table 2−7. PCI System Terminals

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

PDV

GHK

I/O

DESCRIPTION

GRST

177

C11

Global reset. When the global reset is asserted, the GRST signal causes the PCI1520 to place all output

buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is

completely in its default state. For systems that require wake-up from D3, GRST normally is asserted only

during initial boot. PRST should be asserted following initial boot so that PME context is retained during the

transition from D3 to D0. For systems that do not require wake-up from D3, GRST should be tied to PRST.

When the SUSPEND mode is enabled, the device is protected from GRST, and the internal registers are

preserved. All outputs are placed in a high-impedance state.

PCLK

182

C10

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the

rising edge of PCLK.

PRST

168

C13

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1520 to place all output buffers in a

high-impedance state and reset internal registers. When PRST is asserted, the device can generate the PME

signal only if it is enabled. After PRST is deasserted, the PCI1520 is in a default state.

When the SUSPEND mode is enabled, the device is protected from PRST, and the internal registers are

preserved. All outputs are placed in a high-impedance state.

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