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ESDA05 датащи(PDF) 2 Page - Shanghai Leiditech Electronic Technology Co., Ltd |
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ESDA05 датащи(HTML) 2 Page - Shanghai Leiditech Electronic Technology Co., Ltd |
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2 / 5 page ![]() 1-3 Reliability testing procedures Reliability parameter Test Test methods and remarks Test requirement Pulse current capability Imax 8/20 ㎲ IEC 1051-1, Test 4.5. 10 pulses in the same direction at 2 pulses per minute at maximum peak current d Vn/Vn≤ 10% no visible damage Electrostatic discharge capability ESD C=150 pF, R=330 Ω IEC 1000-4-2 Each 10 times in positive/negative direction in 10 sec at 8KV contact discharge (Level 4) d Vn/Vn≤ 10% no visible damage Environmenta l reliability Thermal shock IEC 68-2-14 Condition for 1 cycle Step 1 : Min. –40℃, 30±3 min. Step 2 : Max. +125 ℃, 30±3 min. Number of cycles: 30 times d Vn/Vn≤ 5% no visible damage Low temperature IEC 68-2-1 Place the chip at -40 ±5℃ for 1000± 12hrs. Remove and place for 24 ±2hrs at room temp. condition, then measure d Vn/Vn≤ 5% no visible damage High temperature IEC 68-2-2 Place the chip at 125 ±5℃ for 1000± 24hrs. Remove and place for 24 ±2hrs at room temp. condition, then measure d Vn/Vn≤ 5% no visible damage Heat resistance IEC 68-2-3 Apply the rated voltage for 1000 ±48hrs at 85 ±3℃. Remove and place for 24±2hrs at room temp. condition, then measure d Vn/Vn≤ 5% no visible damage Humidity resistance IEC 68-2-30 Place the chip at 40 ±2℃ and 90 to 95% humidity for 1000 ±24hrs. Remove and place for 24 ±2hrs at room temp. condition, then measure d Vn/Vn≤ 10% no visible damage Pressure cooker test Place the chip at 2 atm, 120 ℃, 85%RH for 60 hrs. Remove and place for 24 ± 2hrs at room temp. condition, then measure d Vn/Vn≤ 10% no visible damage ESDA05 Rev : www.leiditech.com 01.06.2018 2/5 |
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