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LT6372-1

Rev. 0

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THEORY OF OPERATION

The LT6372-1 is an improved version of the classic three op

amp instrumentation amplifier topology that incorporates

features to improve accuracy and simplify interfacing to

ADCs. Laser trimming and proprietary monolithic construc-

tion allow for tight matching and extremely low drift of

circuit parameters over the specified temperature range.

Refer to the Simplified Block Diagram to aid in understand-

ing the following circuit description. The collector currents

in Q1 and Q2 as well as I1 and I4 are trimmed to minimize

input offset voltage drift, thus assuring a high level of per-

formance. R1 and R2 are trimmed to an absolute value of

12.1k to assure that the gain can be set accurately (0.12%

at G = 100) with only one external resistor, RG. The value of

RG determines the transconductance of the preamp stage.

As RG is reduced to increase the programmed gain, the

transconductance of the input preamp stage also increases

to that of the input transistors Q1 and Q2. This causes the

open-loop gain to increase when the programmed gain is

increased, reducing the input related errors and noise. The

input voltage noise at high gains is determined only by Q1

and Q2. At lower gains the noise of the difference amplifier

and preamp gain setting resistors may increase the noise.

The gain bandwidth product is determined by C1, C2 and

the preamp transconductance, which increases with pro-

grammed gain. Therefore, the bandwidth is self-adjusting

and does not drop directly proportional to gain.

The input transistors Q1 and Q2 offer excellent matching,

drift and noise performance, which is due to using a pro-

prietary high performance process, as well as low input

bias current due to the high beta of these input devices.

The input bias current is further reduced by trimming I3

and I6. The collector currents in Q1 and Q2 are held con-

stant due to the feedback through the Q1-A1-R1 loop and

Q2-A2-R2 loop. The action of the amplifier loops impresses

the differential input voltage across the external gain set

resistor RG. Since the current that flows through RG also

flows through R1 and R2, the ratios provide a gained-up

differential voltage,

= 1+

+ R2

to the difference amplifier A3. The difference amplifier

removes the common mode voltage and provides a sin-

gle-ended output voltage referenced to the average of the

voltages on REF1 and REF2. This split reference resistor

configuration allows the output voltage to be easily level

shifted to the center of an ADCs input range without exter-

nal components. The offset voltage of the difference ampli-

fier is trimmed to minimize output offset voltage drift, thus

assuring a high level of performance, even in low gains.

Resistors R5 to R9 are trimmed to maximize CMRR and

minimize gain error. The resulting gain equation is:

= 1+

24.2k

Solving for the gain set resistor gives:

RG =

24.2k

G – 1

Table 1showsappropriate1%resistorvaluesforavarietyofgains.

Table 1. LT6372-1 Gain and RG Lookup.

Resulting Gains for Various 1% Standard Resistor Values

Gain

Standard 1% Resistor Value (Ω)

–

1.996

24.3k

5.007

6.04k

10.06

2.67k

20.06

1.27k

50.69

487

100.6

243

201

121

497.9

48.7

996.9

24.3

Convenient Integer Gains Using Various Standard 1% Resistor Values

Integer Gain

Standard 1% Resistor Value (Ω)

–

12.1k

1.21k

1.1k

122

200

201

121

221

110

243

100

1211 (Note 2)

Additionally, The LT6372-1 has two integrated output

voltage clamps which can be used to limit the voltage

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