AD4682 datasheet(21/30 Pages) AD

21 / 30 page

Data Sheet

AD4682/AD4683

Rev. 0 | Page 21 of 30

INTERFACE

The interface to the AD4682 and the AD4683 is via an SPI. The

interface consists of the CS, SCLK, SDOA, SDOB/ALERT, and SDI

pins. Multifunction pin names may be referenced by their relevant

function only.

The CS signal frames a serial data transfer and initiates an ADC

conversion process. The falling edge of CS puts the track-and-

hold into hold mode, at which point the analog input is sampled,

and the bus is taken out of three-state.

The SCLK signal synchronizes data in and out of the devices via

the SDOA, SDOB, and SDI signals. A minimum of 16 SCLKs

are required for a write to or read from a register. The minimum

number of SCLKs for a conversion read is dependent on the

resolution of the devices and the configuration settings (see

Table 11).

The ADC conversion operation is driven internally by an

on-board oscillator and is independent of the SCLK signal.

The AD4682 and the AD4683 have two serial output signals,

SDOA and SDOB. To achieve the highest throughput of the

devices, use both SDOA and SDOB, 2-wire mode, to read

conversion results. If a reduced throughput is required or

oversampling is used, it is possible to use 1-wire mode, SDOA

signal only, for reading conversion results. Programming the

SDO bit in the CONFIGURATION2 register configures 2-wire

mode or 1-wire mode.

Configuring a cyclic redundancy check (CRC) operation for SPI

reads or SPI writes alters the operation of the interface. Consult

the relevant CRC Read, CRC Write, and CRC Polynomial

sections to ensure proper operation.

READING CONVERSION RESULTS

The CS signal initiates the conversion process. A high to low

transition on the CS signal initiates a simultaneous conversion

of both ADCs, ADC A and ADC B. The AD4682 and the

AD4683 have a one-cycle readback latency. Therefore, the

conversion results are available on the next SPI access. Take the

CS signal low, and the conversion result clocks out on the serial

output pins. The next conversion also initiates at this point.

The conversion result shifts out of the device as a 16-bit result

for the AD4682 and the AD4683. The MSB of the conversion

result shifts out on the CS falling edge. The remaining data

shifts out of the device under the control of the SCLK input.

The data shifts out on the rising edge of the SCLK, and the data

bits are valid on both the falling edge and the rising edge. After

the final SCLK falling edge, take CS high again to return the

SDOA and SDOB/ALERT pins to a high impedance state.

The number of SCLK cycles to propagate the conversion results

on the SDOA and SDOB/ALERT pins is dependent on the serial

mode of operation configured and if resolution boost mode is

enabled (see Figure 40 and Table 11 for details). If CRC reading

is enabled, this reading requires additional SCLK pulses to

propagate the CRC information (see the CRC section for more

details).

As the CS signal initiates a conversion and frames the data, any

data access must be completed within a single frame.

Table 11. Number of SCLK Cycles, n, Required for Reading

Conversion Results

Interface

Configuration

Resolution

Boost Mode

CRC Read

SCLK Cycles

2-Wire

Disabled

Enabled

Disabled

Enabled

1-Wire

Disabled

Enabled

Disabled

Enabled

SCLK

CONVERSION RESULTS

SDOx

1CONSULT TABLE 11 FOR VALUES FOR n, THE NUMBER OF SCLK PULSES REQUIRED.

Figure 40. Reading Conversion Results

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