ES9028PRO datasheet(15/57 Pages) ESS

15 / 57 page

July 6, 2020

CONFIDENTIAL INFORMATION v3.6

ES9028PRO 32-Bit HyperStream® II 8-Channel Audio DAC

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643-

8800 • Fax (408) 643-8801

Note: Multi-byte registers use little-endian byte ordering scheme with the least significant byte stored at the lowest register

address and most significant byte stored at the highest register address.

Bits

[7:4]

[3:2]

[1]

[0]

Mnemonic

osc_drv

clk_gear

reserved

soft_reset

Default

4’b0000

2’b00

1’b0

Bit

Mnemonic

Description

[7:4]

osc_drv

Oscillator drive specifies the bias current to the oscillator pad.

•

4’b1111: shut down the oscillator

•

4’b1110: ¼ bias

•

4’b1100: ½ bias

•

4’b1000: ¾ bias

•

4’b0000: full bias (default)

[3:2]

clk_gear

Configures a clock divider network that can reduce the power

consumption of the chip by reducing the clock frequency supplied to

both the digital core and analog stages.

•

2'b00: MCLK = XIN (default)

•

2'b01: MCLK = XIN / 2

•

2'b10: MCLK = XIN / 4

•

2'b11: MCLK = XIN / 8

[1]

reserved

[0]

soft_reset

Software configurable hardware reset with the ability to reset the design

to its initial power-on configuration.

•

1’b1: resets the SABRE DAC to its power-on defaults

•

1’b0: normal operation (default)

Note

: This register will always read as “1’b0” as the power-on default

for this register is “1’b0”. A reset can be verified by checking the status

of other modified registers.

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