DWM3000 Datasheet

© Qorvo 2020

Preliminary

Version 0.1

Page 6

1.3 SPI Host Interface

The host interface to DWM3000 is a 4-wire SPI-compatible slave. The assertion of SPICSn low by the SPI

master indicates the beginning of a transaction.

The SPI interface is used to read and write registers in the DW3110 device. All data and address transfer on the

SPI is most significant bit first. All address bytes are transmitted with MSB first, and all data is transmitted

commencing with lowest addressed byte.

•

Assertion low of SPICSn initialises transaction.

•

De-assertion high of SPICSn ends the SPI transaction.

•

The device supports direct and per-byte sub-addressing access to the full register space.

•

Efficient block data reading/writing is allowed. Continuous, long transactions can be carried out while the

addressed location is auto-incremented on the DW3110 side.

The SPIMISO I/O is required to go open-drain when SPICSn is de-asserted, to allow interoperation with other

slaves on the SPI bus. SPI daisy chaining is not supported. This is the mode where the MISO, MOSI lines are

passed through a device when it is not chip selected.

1.3.1 SPI Timing Parameters

The SPI slave complies with the Motorola SPI protocol within the constraints of the timing parameters listed in

Table 1 and illustrated in Figure 3 and Figure 4.

SPICSn

SPICLK

SPIMISO

SPIMOSI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit 7 Bit 6 Bit 5

7

6

5

Figure 3: SPI Timing Diagram

SPICSn

SPICLK

SPIMISO

SPIMOSI

7

6

5

Bit 7

Bit 6

Bit 5

Figure 4: SPI Detailed Timing Diagram

Parameter

Min

Typ Max

Unit

Description

3

ns

SPI select asserted low to valid slave output data.

3

ns

SCLK low to valid slave output data.

14

ns

Master data setup time.

2

ns

Master data hold time.

27

ns

LSB last byte to MSB next byte.

3

ns

SPI select deasserted high to MISO tristate.

14

ns

Start time; time from select asserted to first SCLK.

24

ns

Last SCLK to SEL_n deasserted.

24

ns

Idle time between consecutive accesses.

38

MHz

SPI CLK Fmax @1.8V VDD1, 25C, SPI mode 0.

Table 1: SPI Timing Parameters