After setting SDP, any attempt to write to the device without the 3‑byte command sequence will start the internal write

operations.

DEVICE IDENTIFICATION: An extra 128 bytes of EEPROM memory are available to the user for device

identification. By raising A9 to 12V ± 0.5V and using address locations 1FF80H to 1FFFFH, the bytes may be written

to or read from in the same manner as the regular memory array.

OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6‑byte software code. See Software Chip

Erase application note for details.

5.1

Operating Modes

Table 5-1. Operating Modes

Mode

CE

OE

WE

I/O

Read

Standby/Write Inhibit

X(2)

X

High-Z

Write Inhibit

X

X

Write Inhibit

X

X

Output Disable

X

X

High-Z

Note: 

1.

Refer to AC Programming Waveforms.

2.

5.2

AC Read Characteristics

Table 5-2. AC Read Characteristics

Parameter

Symbol

AT28C010‑12

AT28C010‑15

AT28C010‑20

AT28C010‑25

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Address to

Output Delay

—

120

—

150

—

200

—

250

ns

CE to Output

Delay

—

120

—

150

—

200

—

250

ns

OE to Output

Delay

0

50

0

55

0

55

0

55

ns

CE or OE to

Output Float

0

50

0

55

0

55

0

55

ns

Output Hold

from OE, CE

or Address,

whichever

occurred first

0

0

0

0

ns

CE Pulse

High Time

50

—

50

—

50

—

50

—

ns

AT28C010

Device Operation

DS20006311A-page 10