FTD6821 datasheet(15/17 Pages) FS

15 / 17 page

Function Description(Cont.)

Figure 4:Power Lost VS Load Current

1. The VIN quiescent current is due to two components:

the DC bias current as given in the electrical

characteristics and the internal main switch and

synchronous switch gate charge currents. The gate

charge current results from switching the gate

capacitance of the internal power MOSFET switches.

Each time the gate is switched from high to low to high

again, a packet of charge, dQ, moves from VIN to

ground. The resulting dQ/dt is the current out of VIN that

is typically larger than

the DC bias current. In continuous mode, IGATECHG

=f(QT + QB) where QT and QB are the gate charges of

the internal top and bottom switches. Both the DC bias

and gate charge losses are proportional to VIN and

thustheir effects will be more pronounced at higher

supply voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In

continuous mode, the average output current flowing

through inductor L is “chopped” between the main switch

and the synchronous switch. Thus, the series resistance

looking into the SW pin is a function of both top and

bottom MOSFET RDS(ON) and the duty cycle (DC) as

follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs

can be obtained from the Typical Performance

Charateristics curves. Thus, to obtain I2R losses, simply

add RSW to RL and multiply the result by the square of

the average output current. Other losses including CIN

and COUT ESR dissipative losses and inductor core

losses generally account for less than 2% total

additional loss.

Thermal Considerations

In most applications the FTD6821 does not dissipate

much heat due to its high efficiency. But, in applications

where the FTD6821 is running at high ambient

temperature with low supply voltage and high duty

cycles, such as in dropout, the heat dissipated may

exceed the maximum junction temperature of the part. If

the junction temperature reaches approximately 150°C,

both power switches will be turned off and the SW node

will become high impedance.

To avoid the FTD6821 from exceeding the maximum

junction temperature, the user will need to do some

thermal analysis. The goal of the thermal analysis is to

determine whether the power dissipated exceeds the

maximum junction temperature of the part. The

temperature rise is given by:

TR = (PD)(qJA)

where PD is the power dissipated by the regulator and

qJA is the thermal resistance from the junction of the die

to the ambient temperature.

The junction temperature, TJ, is given by:TJ = TA + TR

where TA is the ambient temperature.

As an example, consider the FTD6821 in dropout at an

input voltage of 2.7V, a load current of 800mA and an

ambient temperature of 70°C. From the typical

performance graph of switch resistance, the RDS(ON)

of the P-channel switch at 70°C is approximately 0.52W.

2013.01. 28

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SEMICONDUCTOR

TECHNICAL D ATA

FTD6821

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