XIO2000AI datasheet(95/165 Pages) TI

95 / 165 page

Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.66 Clock Control Register

This register enables and disables the PCI clock outputs (CLKOUT). See Table 4−40 for a complete

description of the register contents.

PCI register offset:

D8h

Read-only, Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 4−40. Clock Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

RSVD

Reserved. Returns 0b when read.

6†

CLOCK6_DISABLE

Clock output 6 disable. This bit disables secondary CLKOUT6.

0 = Clock enabled (default)

1 = Clock disabled

5†

CLOCK5_DISABLE

Clock output 5 disable. This bit disables secondary CLKOUT5.

0 = Clock enabled (default)

1 = Clock disabled

4†

CLOCK4_DISABLE

Clock output 4 disable. This bit disables secondary CLKOUT4.

0 = Clock enabled (default)

1 = Clock disabled

3†

CLOCK3_DISABLE

Clock output 3 disable. This bit disables secondary CLKOUT3.

0 = Clock enabled (default)

1 = Clock disabled

2†

CLOCK2_DISABLE

Clock output 2 disable. This bit disables secondary CLKOUT2.

0 = Clock enabled (default)

1 = Clock disabled

1†

CLOCK1_DISABLE

Clock output 1 disable. This bit disables secondary CLKOUT1.

0 = Clock enabled (default)

1 = Clock disabled

0†

CLOCK0_DISABLE

Clock output 0 disable. This bit disables secondary CLKOUT0.

0 = Clock enabled (default)

1 = Clock disabled

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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