TPS2340A

SLUS528A – MARCH 2002 – REVISED AUGUST 2002

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APPLICATION INFORMATION

NAND tree test

All bi-directional pins are tri-stated for input mode during the NAND Tree test except SIDO. All inputs except

TEST should be forced low then forced high, one signal at a time, in the order listed below. The TEST pin is the

last signal in the chain and is forced high then low. The NAND result is driven on the SIDO output pin as shown

in the timing diagram in Figure 5.

Table 12. NAND Tree Order

NAND TREE ORDER

PIN NO.

1

SIDI

20

2

SODO

19

3

SWA

46

4

SWB

14

5

PRSNT1A

37

6

PRSNT1B

24

7

PRSNT2A

36

8

PRSNT2B

25

9

BUTTONA

45

10

BUTTONB

15

11

M66ENA

34

12

M66ENB

27

13

PCI–XCAPA

50

14

PCI–XCAPB

11

15

SODI

42

16

SOC

17

17

SOR

40

18

SORR

21

19

SOLC

39

20

SORLC

22

21

BUSENA

32

22

BUSENB

29

23

CLKENA

33

24

CLKENB

28

25

RESETA

35

26

RESETB

26

27

PWRLEDA

48

28

PWRLEDB

12

29

ATTLEDA

47

30

ATTLEDB

13

31

SIL

16

32

SIC

44

33

TEST

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