TMS320F28075PZPQ datasheet(92/196 Pages) TI

92 / 196 page

TMS320F28076, TMS320F28075

SPRS902I – OCTOBER 2014 – REVISED JUNE 2020

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Product Folder Links: TMS320F28076 TMS320F28075

Specifications

Table 5-47 shows the parasitic capacitance on each channel. Also, enabling a comparator adds

approximately 1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative

comparator inputs.

(1)

The increased capacitance is due to VDAC functionality.

Table 5-47. Per-Channel Parasitic Capacitance

ADC CHANNEL

Cp (pF)

COMPARATOR DISABLED

COMPARATOR ENABLED

ADCINA0

12.9

N/A

ADCINA1

10.3

N/A

ADCINA2

5.9

7.3

ADCINA3

6.3

8.8

ADCINA4

5.9

7.3

ADCINA5

6.3

8.8

ADCINB0(1)

117.0

N/A

ADCINB1

10.6

N/A

ADCINB2

5.9

7.3

ADCINB3

6.2

8.7

ADCINB4

5.2

N/A

ADCINB5

5.1

N/A

ADCIND0

5.3

6.7

ADCIND1

5.7

8.2

ADCIND2

5.3

6.7

ADCIND3

5.6

8.1

ADCIND4

4.3

N/A

ADCIN14

8.6

10.0

ADCIN15

9.0

11.5

This input model should be used along with actual signal source impedance to determine the acquisition

window duration. See the Choosing an Acquisition Window Duration section of the TMS320F2807x

Microcontrollers Technical Reference Manual for more information.

The user should analyze the ADC input setting assuming worst-case initial conditions on Ch. This will

require assuming that Ch could start the S+H window completely charged to VREFHI or completely

discharged to VREFLO. When the ADC transitions from an odd-numbered channel to an even-numbered

channel, or vice-versa, the actual initial voltage on Ch will be close to being completely discharged to

VREFLO. For even-to-even or odd-to-odd channel transitions, the initial voltage on Ch will be close to the

voltage of the previously converted channel.

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