IPS2200 Datasheet

Jan.19.21

Page 28

Function

Programming Options

I2C interface

Slave address, I2C mode with address select or with interrupt

Diagnostic signaling on high speed interface

Enable/disable: Output pins are pulled low or high in diagnostic state

Security lock function

Register access R/W / read-only

RF front end integration cycles

Number of integration cycles; adjust noise vs. speed

Receiver overall gain

Overall gain coarse adjustment

Sine, cosine channel gain

Amplitude mismatch correction, fine adjustment

Sine, cosine offset

Pre-adjustment of input offsets

Tx oscillator

Bias current, optimization of coil performance

Time base counter

Measurement of Tx oscillator frequency, upper/lower frequency alarm

Interrupt

Enable/disable interrupt events

16. Diagnostics

The diagnostics described in Table 22 are performed on the chip level and are flagged in corresponding

registers if a fault detection occurs. Each of these diagnostic functions can be enabled or disabled to generate

an interrupt event at the CSN_IRQN output. In addition, an interrupt event can also be signaled through the high

speed interface pins (SIN, SINN, COS, COSN; see Table 2) by putting them into the diagnostic state.

Alarm types marked as “Static” will remain set while the error persists and are cleared only by power-on-reset

(POR); alarm types marked as “Temporary” will be cleared when the source of the error is removed.

Diagnostic flags marked as “Continuous” are continuously tested; diagnostic flags marked as “Start-up” are

checked at start-up only.

Table 22. Diagnostic Features

Diagnostic Flag

Type

Active

Description

VDD over-voltage

Temporary

Continuous

If the external supply voltage exceeds the maximum limit of typical +10%,

this flag is asserted. To avoid a flag toggling, a comparator hysteresis is

implemented. See Table 6 for alarm levels in 3.3V Mode and Table 7 for

alarm levels in 5V Mode.

VDD under-voltage

Temporary

Continuous

If the external supply voltage falls short of the minimum limit of typical -10%,

this flag is asserted. To avoid a flag toggling, a comparator hysteresis is

implemented. See Table 6 for alarm levels in 3.3V Mode and Table 7 for

alarm levels in 5V Mode.

Data access fail

Temporary

Continuous

Chip internal failure.

Protocol integrity fail

Temporary

Continuous

Failure in the I2C/SPI data transfer.

Shadow register DED

Static

Continuous

Shadow register bank double-bit error detection.

Shadow register SED

Temporary

Continuous

Shadow register bank single-bit error detection. Each single-bit error

detection triggers a single-bit error correction (SEC) of the register output.

Nonvolatile memory

DED

Static

Start-up

NVM double-bit error detection. Each individual addressed word is checked

and flagged for bit error.

Nonvolatile memory

SED

Temporary

Start-up

NVM single-bit error detection. Each individual addressed word is checked

and flagged for bit errors.

Each single-bit error detection triggers a single-bit error correction (SEC) of

the NVM output.

LC oscillator failure

Temporary

Continuous

This flag is set when the LC oscillator frequency is out of range. The

frequency range is programmable; see section 16.2 for details.

LC oscillator stuck

Temporary

Continuous

This flag is set when the LC oscillator stops running.

VDDA under-voltage or

CSN_IRQN over-voltage

or SIO_SDA over-

voltage

Temporary

Continuous

This flag is set when the internally regulated analog supply voltage VDDA

falls below specified limits or when an over-voltage on pins CSN_IRQN or

SIO_SDA is detected.

See Table 6 or Table 7 for VDDA alarm levels and Table 4 for IRQN_CSN

and SIO_SDA over-voltage alarm levels.

Low amplitude

Temporary

Continuous

In the Incremental Digital Mode, a minimum signal level must be defined

(gain factor) for a valid output function. If this flag is asserted, the gain factor

must be increased.

Internal bus failure

Temporary

Continuous

Chip internal failure.