STPMIC1DPQR datasheet(61/140 Pages) STMICROELECTRONICS

61 / 140 page

NVM read operation

NVM read operation is fully managed by the STPMIC1.

For each read operation, the STPMIC1 automatically loads the 64-bit NVM content into NVM shadow registers

(see Table 64. NVM shadow register map ). It means that shadow register content is a copy of NVM content.

When the STPMIC1 power supply is connected (VIN > VPOR_VIN_Rise), the STPMIC1 state machine goes to

PRELOAD_NVM state (see Section 5.2 Functional state machine). In this state, a NVM read operation is

performed to check if the STPMIC1 should start up automatically depending on AUTO_TURN_ON NVM bit value.

If AUTO_TURN_ON bit is not set, the STPMIC1 goes to OFF-state; else the STPMIC1 continues automatically by

power-up procedure.

Before each POWER_UP procedure, NVM read operation is performed in CHECK&LOAD state. NVM content is

loaded into shadow registers. Additionally, the STPMIC1 initializes BUCK and LDO control registers with values

pre-defined in NVM (see Table 64. NVM shadow register map ) and configure POWER_UP and POWER_DOWN

sequence of regulators.

NVM write operation (STPMIC1 customization)

NVM write operation can be performed multiple times (see NVMEND) by I2C interface.

NVM write operation generic sequence:

Apply VIN to the application: STPMIC1 goes to POWER_ON state(1)

Write NVM shadow registers with expected customization values

Initiate a “NVM program operation” command - write NVM_CMD[1:0] = ‘01’ in Section 6.6.2 NVM control

Wait for NVM write operation to be completed: wait for NVM_BUSY becomes 0 in Table 62. NVM_SR

(Optional): check new NVM content by initiating a NVM read operation: write NVM_CMD[1:0] = ‘10’ and wait

for NVM_BUSY becomes 0

1. The STPMIC1 has AUTO_TURN_ON bit set by default to power up automatically. This is to allow NVM write operation

without generating turn-ON conditions.

The following conditions should be fulfilled to allow NVM write operation:

•

VIN must be minimum 3.8 V

•

The STPMIC1 must be in POWER_ON state (NVM write operation is ignored in OFF-state)

Writing into NVM shadow registers does not affect NVM content until NVM write operation is executed.

WARNING: If VIN goes below 3.8 V during write operation, NVM content integrity may be corrupted and the

STPMIC1 may not start up anymore.

Change of I2C address

Special attention must be given when new I2C address needs to be programmed.

When different I2C address is written in Section 6.7.8 NVM device address shadow register (I2C_ADDR_SHR),

this new address becomes effective immediately and next I2C transaction must already use this new device

address.

If a “NVM write operation” is not performed following I2C address change in shadow register, previously

programmed I2C address is loaded from NVM during next POWER_UP sequence.

STPMIC1

Programming

DS12792 - Rev 7

page 61/140

STPMIC1DPQR датащи(PDF) 61 Page - STMicroelectronics

STPMIC1DPQR датащи(HTML) 61 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL