6.4

Read operations on chip enable register

Read operations are performed independently of the state software write protect bit (SWP).

Following a start condition the bus master sends a device select code with the R/W bit (RW) set to 0. The device

acknowledges this and waits for the address bytes where the register is located. The device responds to each

address byte with an acknowledge. Then, the bus master sends another start condition, and repeats the device

select code with the RW bit set to 1. The device acknowledges this, and outputs the contents of the chip enable

register.

To terminate the stream of data byte, the bus master must not acknowledge the byte, and must generate a stop

condition, as shown in Figure 10.

After the successful completion of a random address read operation, the device internal address counter is not

incremented by one, to point to the next byte address. Reading more than one byte will loop on reading the chip

enable register value.

Reading the chip enable register is performed with a random read instruction at address 1xxx.xxxx.xxxx.xxxxb:

•

Bits b7, b6, b5, b4 of the chip enable register content are read as 0, 0, 0, 0.

•

The configurable device address bits b3, b2, b1 are described in Section 4.1 Chip enable register.

•

The software write protection bit b0 is defined in Section 4.1 Chip enable register.

The chip enable address value can be checked by sending the device select code.

•

If the chip enable address b3, b2, b1 sent in the device select code is matching with the C2, C1 and C0

values, device will send an acknowledge.

•

Otherwise, device will answer NoACK.

Byte addr

Byte addr

ACK

R/W

ACK

ACK

ACK

Data out

NO ACK

R/W

1.

The seven most significant bits of the device select code of a random read (in the first and fourth bytes) must

be identical.

M24128X-FCU

Read operations on chip enable register

DS12680 - Rev 2

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