A6986H datasheet(49/71 Pages) STMICROELECTRONICS

49 / 71 page

The device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it is able to synchronize

to a clock signal in the range 475 kHz - 2.2 MHz (see Figure 48. Synchronization pulse definition).

As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the slope compensation

is dimensioned accordingly with FSW resistors so it is important to limit the switching operation around a working

point close to the selected oscillator frequency (FSW resistor).

As a consequence, to guarantee the full output current capability and to prevent the subharmonic oscillations, the

MASTER may limit the driving frequency range within ± 5% of the selected frequency.

A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the peak current capability

(see IPK parameter in Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise

specified.) since the internal slope compensation signal may be saturated.

The device keeps operating in slave mode as far as the master is able to drive the SYNCH pin faster than 275

kHz, otherwise the A6986H goes back into MASTER mode at the programmed RFSW oscillator frequency after

successfully driving one pulse 250 kHz typ. (see Figure 50. Slave-to-master mode transition) in the SYNCH line.

Figure 50. Slave-to-master mode transition

The external master can force a latched SLAVE mode driving the SYNCH pin low at power-up, before the soft-

start begins the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is

triggered regardless FSW resistor value, that otherwise counts to design the slope compensation. The same

considerations above are also valid.

The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see

Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.):

•

Low level < VSYN THL = 0.7 V sinking 5 mA

•

High level > VSYN THH = 1.2 V sourcing 0.7 mA

A6986H

Synchronization (LNM)

DS12861 - Rev 3

page 49/71

A6986H датащи(PDF) 49 Page - STMicroelectronics