853014BG

www.icst.com/products/hiperclocks.html

REV. C MAY 13, 2005

11

Integrated

Circuit

Systems, Inc.

ICS853014

This application note provides general design guide using

ICS853014 LVPECL buffer.

Figure 6 shows a schematic example

of the ICS853014 LVPECL clock buffer. In this example, the in-

put is driven by an LVPECL driver. CLK_SEL is set at logic high

to select PCLK1/nPCLK1 input.

R5

50

Zo = 50

R10

50

C5

0.1u

R4

50

C2

0.1u

R1

50

Zo = 50

C4

0.1u

+

-

C1

0.1u

+

-

R7

50

LVPECL Driv er

C3

0.1u

Zo = 50

Zo = 50

R12

1K

U1

ICS853014

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

Q4

nQ4

VEE

CLK_SEL

PCLK0

nPCLK0

VBB

PCLK1

VCC

nEN

VCC

nPCLK1

R11

1K

R6

50

3.3V

3.3V

R2

50

Zo = 50

3.3V

R9

50

R3

50

Zo = 50

3.3V