7 / 14 page
MDT2030
This specification are subject to be changed without notice. Any latest information
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P. 6
2004/1
Ver. 1.3
Register
Address
Power-On Reset
/MCLR or WDT Reset
PORT A
05h
- - - - xxxx
- - - - uuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
Note : u
＝unchanged, x＝unknown, - ＝unimplemented, read as “0”
#
＝value depends on the condition of the following table
Condition
Status: bit 4
Status: bit 3
/MCLR reset (not during SLEEP)
u
u
/MCLR reset during SLEEP
1
0
WDT reset (not during SLEEP)
0
1
WDT reset during SLEEP
0
0
9. Instruction Set :
Instruction Code
Mnemonic
Operands
Function
Operating
Status
010000 00000000
NOP
No operation
None
010000 00000001
CLRWT
Clear Watchdog timer
0
→WT
TF, PF
010000 00000010
SLEEP
Sleep mode
0
→WT, stop OSC
TF, PF
010000 00000011
TMODE
Load W to TMODE register
W
→TMODE
None
010000 00000100
RET
Return
Stack
→PC
None
010000 00000rrr
CPIO
R
Control I/O port register
W
→CPIO r
None
010001 1rrrrrrr
STWR
R
Store W to register
W
→R
None
011000 trrrrrrr
LDR R, t
Load register
R
→t
Z
111010 iiiiiiii
LDWI
I
Load immediate to W
I
→W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3)
↔R(4~7)]
→t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1
→t
Z
011010 trrrrrrr
INCRSZ R, t
Increment register, skip if zero
R + 1
→t
None
011011 trrrrrrr
ADDWR R, t
Add W and register
W + R
→t
C, HC, Z
011100 trrrrrrr
SUBWR R, t
Subtract W from register
R
﹣W→t or
(R+/W+1
→t)
C, HC, Z
011101 trrrrrrr
DECR R, t
Decrement register
R
﹣1→t
Z
011110 trrrrrrr
DECRSZ R, t
Decrement register, skip if zero
R
﹣1→t
None
010010 trrrrrrr
ANDWR R, t
AND W and register
R
∩ W→t
Z
110100 iiiiiiii
ANDWI
i
AND W and immediate
i
∩ W→W
Z
010011 trrrrrrr
IORWR R, t
Inclu. OR W and register
R
∪ W→t
Z
110101 iiiiiiii
IORWI
i
Inclu. OR W and immediate
i
∪ W→W
Z
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