TAS2764YBHT datasheet(21/107 Pages) TI

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default to 0 dB. It should be noted that these levels may not be achievable because of analog clipping in the

amplifier, so they should be used to convey gain only.

Equation 1 below calculates amplifier output voltage:

VAMP= INPUT+ADVC+AAMP

(1)

where

• VAMP is the amplifier output voltage in dBV

• INPUT is the digital input amplitude as a number of dB with respect to 0 dBFS

• ADVC is the digital volume control setting as a number of dB

• AAMP is the amplifier output level setting as a number of dBV

The digital volume control (DVC) is configurable from 0 dB to -100 dB in 0.5 dB steps by setting the

DVC_LVL[7:0] register bits. Settings greater than C8h are interpreted as mute. When a change in digital volume

control occurs, the device ramps the volume to the new setting based on the DVC_RAMP_RATE[1:0] register

bits status. If DVC_RAMP_RATE[1:0] bits are set to 2'b11 the volume ramping is disabled. This setting can be

used to speed up startup, shutdown and digital volume changes when volume ramping is handled by the system

master.

The Class-D amplifier uses a closed-loop architecture, so the gain does not depend on power supply. The

approximate threshold for the onset of analog clipping is calculated in Equation 2.

(2)

where

• VPK is the maximum peak un-clipped output voltage in V

• VSUP is the power supply of class-D output stage

• RL is the speaker load in Ω

• RP is the parasitic resistance on PCB (routing, filters) in Ω

• RFET is the power stage total resistance (HS FET, LS FET, Sense Resistor, bonding, packaging) in Ω

When VBAT1S supplies class-D output stage typical RFET value is 1 Ω. For PVDD supply RFET typical value is

0.5 Ω.

8.4.2.3.1 Safe Mode

The safe mode is a single bit that will enable 18 dB attenuation in the forward path. It is similar to setting the

DVC_LVL[7:0] register bits to a setting of 24h (-18dB). When the SMODE_EN bit is set to high, the

DVC_LVL[7:0] register bits will be ignored and volume ramping disabled.

8.4.2.4 VBAT1S Supply

The TAS2764 can operate with or without a VBAT1S supply. When configured without a VBAT1S supply, the

PVDD voltage will be used with an internal LDO to generate this supply voltage. A decoupling capacitor should

still be populated as recommended in Table 9-1. In this case, VBAT1S_MODE bit should be set to high before

transitioning from software shutdown. More details about VBAT1S supply modes of operation can be found in

Section 12.1.

8.4.2.5 Low Voltage Signaling (LVS)

The TAS2764 monitors the absolute value of the audio stream.

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TAS2764

SLOS998 – DECEMBER 2020

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