LTC6907 datasheet(21/34 Pages) AD

21 / 34 page

LTC6992-1/LTC6992-2/

LTC6992-3/LTC6992-4

Rev. D

For more information www.analog.com

APPLICATIONS INFORMATION

a large RSET resistor. POL = 0 and NDIV = 4 requires

DIVCODE = 1. Using Table 1, choose the R1 and R2 values

to program DIVCODE = 1.

Step 4: Select RSET

Calculate the correct value for RSET using Equation (1b).

RSET =

1MHz • 50k

4 • 20kHz

= 625k

Since 625k is not available as a standard 1% resistor,

substitute 619k if a 0.97% frequency shift is acceptable.

Otherwise, select a parallel or series pair of resistors such

as 309k and 316k to attain a more precise resistance.

The completed design is shown in Figure 7.

6992 F07

LTC6992-4

MOD

GND

SET

OUT

V+

DIV

976k

DIVCODE = 1

102k

RSET

625k

VMOD

2.25V TO 5.5V

Figure 7. 20kHz PWM Oscillator

Figure 8. Duty Cycle Variation Due to ∆VSET

VMOD (V)

100

0.6

0.2

6992 F08

0.4

0.8

∆VSET = 0mV

∆VSET = 30mV

∆VSET = –30mV

Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator

6992 F09

LTC6992-X

MOD

GND

SET

OUT

V+

DIV

RSET2

RSET1

2.25V TO 5.5V

•

RSET2

RSET1 +RSET2

−

Figure 8 demonstrates the worst-case impact of this varia-

tion (if VSET is at its 0.97V or 1.03V limits).

This error is in addition to the inherent PWM duty cycle

accuracy spec ∆D (±4.5%), so care should be taken if

accuracy at high duty cycles (VMOD near 0.9V) is critical.

Sensitivity to ∆VSET can be eliminated by making VMOD

proportional to VSET. For example, Figure 9 shows a

simple circuit for generating an arbitrary duty cycle. The

equation for duty cycle does not depend on VSET at all.

Duty Cycle Sensitivity to ∆VSET

The output duty cycle is proportional to the ratio of VMOD/

VSET. Since VSET can vary up to ±30mV from 1V it can

effectively gain or attenuate VMOD, as shown below when

∆VSET is added to the equation.

D =

VMOD

0.8 • VSET + ∆VSET

(

)

−

For many designs, the absolute VMOD to duty cycle accu-

racy is not critical. For others, making the simplifying

assumption of ∆VSET = 0V creates the potential for addi-

tional duty cycle error, which increases with VMOD, reach-

ing a maximum of 3.4% if ∆VSET = –30mV.

∆D ≅ −

VMOD

800mV

•

∆VSET

VSET

≅ − DIDEAL +

⎛

⎝

⎜

⎞

⎠

⎟ •

∆VSET

VSET

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